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CYRF6936
WirelessUSBTM LP 2.4 GHz Radio SoC
Features
* 2.4 GHz Direct Sequence Spread Spectrum (DSSS) radio transceiver * Operates in the unlicensed worldwide Industrial, Scientific and Medical (ISM) band (2.400 GHz-2.483 GHz) * 21 mA operating current (Transmit @ -5 dBm) * Transmit power up to +4 dBm * Receive sensitivity up to -97 dBm * Sleep Current <1 A * Operating range: 10m+ * DSSS data rates up to 250 kbps, GFSK data rate of 1 Mbps * Low external component count * Auto Transaction Sequencer (ATS) - no MCU intervention * Framing, Length, CRC16, and Auto ACK * Power Management Unit (PMU) for MCU/Sensor * Fast Startup and Fast Channel Changes * Separate 16-byte Transmit and Receive FIFOs * AutoRateTM - dynamic data rate reception * Receive Signal Strength Indication (RSSI) * Serial Peripheral Interface (SPI) control while in sleep mode * 4 MHz SPI microcontroller interface * Battery Voltage Monitoring Circuitry * Supports coin-cell operated applications * Operating voltage from 1.8V to 3.6V * Operating temperature from 0 to 70C * Space saving 40-pin QFN 6x6 mm package
Applications
* * * * * * * * * * Wireless Keyboards and Mice Wireless Gamepads Remote Controls Toys VOIP and Wireless Headsets White Goods Consumer Electronics Home Automation Automatic Meter Readers Personal Health and Entertainment
Applications Support
See www.cypress.com for development tools, reference designs, and application notes.
Functional Description
The CYRF6936 WirelessUSBTM LP radio is a second generation member of Cypress's WirelessUSB Radio System-On-Chip (SoC) family. The CYRF6936 is interoperable with the first generation CYWUSB69xx devices. The CYRF6936 IC adds a range of enhanced features, including increased operating voltage range, reduced supply current in all operating modes, higher data rate options, and reduced crystal start up, synthesizer settling and link turnaround times.
CYRF6936 Simplified Block Diagram
VIO VBAT L/D VREG VDD VCC PACTL RFP RFN RFBIAS
Power Management
GFSK Modulator
IRQ SS SCK MISO MOSI
SPI
Data Interface and Sequencer RSSI
DSSS Baseband & Framer GFSK Demodulator
Xtal Osc RST XTAL XOUT GND
Synthesizer Block Diagram
Cypress Semiconductor Corporation Document #: 38-16015 Rev. *G
*
198 Champion Court
*
San Jose, CA 95134-1709
* 408-943-2600 Revised April 2, 2007
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CYRF6936
Pin Descriptions
Pin # 13 11 10 30 1 29 25 28 27 24 26 34 Name Type Default RFN RFP RFBIAS PACTL XTAL XOUT SCK MISO MOSI SS IRQ RST I/O I/O O I/O I I/O I I/O I/O I I/O I I I O O I O I Z I I O I Description Differential RF signal to/from antenna Differential RF signal to/from antenna RF I/O 1.8V reference voltage Control signal for external PA, T/R switch, or GPIO 12 MHz crystal Buffered 0.75, 1.5, 3, 6 or 12 MHz clock, PACTL, or GPIO. Tri-states in sleep mode (configure as GPIO drive LOW) SPI clock SPI data output pin (Master In Slave Out), or GPIO (in SPI 3-pin mode). Tri-states when SPI 3PIN = 0 and SS is deasserted SPI data input pin (Master Out Slave In), or SDAT SPI enable, active LOW assertion. Enables and frames transfers Interrupt output (configurable active HIGH or LOW), or GPIO Device reset. Internal 10 kohm pull down resistor. Active HIGH, typically connect through a 0.47 F capacitor to VBAT. Must have RST = 1 event the first time power is applied to the radio. Otherwise the state of the radio control registers is unknown PMU inductor/diode connection, when used. If not used, connect to GND PMU boosted output voltage feedback Decoupling pin for 1.8V logic regulator, connect through a 0.47 F capacitor to GND VBAT = 1.8V to 3.6V. Main supply VCC = 2.4V to 3.6V. Typically connected to VREG I/O interface voltage, 1.8-3.6V Must be connected to GND Connect to GND Ground Ground
37 40 35 6, 8, 38 3, 7, 16 33 19
L/D VREG VDD VBAT VCC VIO RESV
O Pwr Pwr Pwr Pwr Pwr I NC GND GND
2, 4, 5, 9, 14, 15, 18, 17, 20, NC 21, 22, 23, 32, 36, 39, 31 12 E-PAD GND GND
Figure 1. CYRF6936, 40 QFN - Top View
CYRF6936 Top View*
VREG 40 XTAL 1 NC 2 VCC 3 NC 4 NC 5 VBAT 6 VCC 7 VBAT 8 NC 9 RF BIAS 10 11 RFP 12 GND 13 RFN 14 NC 15 NC 16 VCC 17 NC 18 NC 19 RESV 20 NC RST 34 VBAT 38 VDD 35 L/D 37 NC 39 NC 36 NC 32 NC 31 VIO 33
30 PACTL / GPIO 29 XOUT / GPIO 28 MISO / GPIO 27 MOSI / SDAT
CYRF6936 40-lead QFN
26 IRQ / GPIO 25 SCK 24 SS 23 NC 22 NC 21 NC
* E-PAD BOTTOM SIDE
Document #: 38-16015 Rev. *G
Page 2 of 40
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CYRF6936
Functional Overview
The CYRF6936 IC provides a complete WirelessUSB SPI to antenna wireless MODEMs. The SoC is designed to implement wireless device links operating in the worldwide 2.4 GHz ISM frequency band. It is intended for systems compliant with worldwide regulations covered by ETSI EN 301 489-1 V1.41, ETSI EN 300 328-1 V1.3.1 (Europe), FCC CFR 47 Part 15 (USA and Industry Canada) and TELEC ARIB_T66_March, 2003 (Japan). The SoC contains a 2.4 GHz, 1 Mbps GFSK radio transceiver, packet data buffering, packet framer, DSSS baseband controller, Received Signal Strength Indication (RSSI), and SPI interface for data transfer and device configuration. The radio supports 98 discrete 1 MHz channels (regulations may limit the use of some of these channels in certain jurisdictions). The baseband performs DSSS spreading/despreading, Start of Packet (SOP), End of Packet (EOP) detection, and CRC16 generation and checking. The baseband may also be configured to automatically transmit Acknowledge (ACK) handshake packets whenever a valid packet is received. When in receive mode, with packet framing enabled, the device is always ready to receive data transmitted at any of the supported bit rates, enabling the implementation of mixed-rate systems in which different devices use different data rates. This also enables the implementation of dynamic data rate systems that use high data rates at shorter distances or in a low-moderate interference environment or both, and change to lower data rates at longer distances or in high interference environments or both. In addition, the CYRF6936 IC has a Power Management Unit (PMU), which allows direct connection of the device to any battery voltage in the range 1.8V to 3.6V. The PMU conditions the battery voltage to provide the supply voltages required by the device, and may supply external devices. Data Transmission Modes The SoC supports four different data transmission modes: * In GFSK mode, data is transmitted at 1 Mbps, without any DSSS. * In 8DR mode, eight bits are encoded in each derived code symbol transmitted. * In DDR mode, two bits are encoded in each derived code symbol transmitted. (As in the CYWUSB6934 DDR mode). * In SDR mode, one bit is encoded in each derived code symbol transmitted. (As in the CYWUSB6934 standard modes.)
Both 64 chip and 32 chip Pseudo Noise (PN) codes are supported. The four data transmission modes apply to the data after the SOP. In particular the length, data, and CRC16 are all sent in the same mode. In general, lower data rates reduce packet error rate in any given environment. Link Layer Modes The CYRF6936 IC device supports the following data packet framing features: SOP - Packets begin with a two-symbol Start of Packet marker. This is required in GFSK and 8DR modes, but is optional in DDR mode and is not supported in SDR mode; if framing is disabled then an SOP event is inferred whenever two successive correlations are detected. The SOP_CODE_ADR code used for the SOP is different from that used for the "body" of the packet, and if desired may be a different length. SOP must be configured to be the same length on both sides of the link. Length - There are two options for detecting the end of a packet. If SOP is enabled, then the length field should be enabled. GFSK and 8DR must enable the length field. This is the first eight bits after the SOP symbol, and is transmitted at the payload data rate. When the length field is enabled, an End of Packet condition is inferred after reception of the number of bytes defined in the length field, plus two bytes for the CRC16 (when enabled--see the following paragraph). The alternative to using the length field is to infer an EOP condition from a configurable number of successive noncorrelations; this option is not available in GFSK mode and is only recommended when using SDR mode. CRC16 - The device may be configured to append a 16 bit CRC16 to each packet. The CRC16 uses the USB CRC polynomial with the added programmability of the seed. If enabled, the receiver verifies the calculated CRC16 for the payload data against the received value in the CRC16 field. The seed value for the CRC16 calculation is configurable, and the CRC16 transmitted may be calculated using either the loaded seed value or a zero seed; the received data CRC16 is checked against both the configured and zero CRC16 seeds. CRC16 detects the following errors: * Any one bit in error * Any two bits in error (no matter how far apart, which column, and so on) * Any odd number of bits in error (no matter where they are) * An error burst as wide as the checksum itself Figure 2 shows an example packet with SOP, CRC16 and lengths fields enabled, and Figure 3 on page 4 shows a standard ACK packet.
Figure 2. Example Packet Format
P re a m b le n x 16us 2 n d F ra m in g S y m b o l*
P
SOP 1
1 s t F ra m in g S y m b o l*
SOP 2
L e n g th
Packet le n g th 1 B y te P e rio d
P a y lo a d D a ta
C R C 16
*N o te :3 2 o r 6 4 u s
Document #: 38-16015 Rev. *G
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CYRF6936
Figure 3. Example ACK Packet Format
P r e a m b le n x 16us 2 n d F r a m in g S y m b o l*
P
SOP 1
1 s t F r a m in g S y m b o l*
SOP 2
C R C 16
C R C f ie ld f r o m r e c e iv e d p a c k e t . 2 B y t e p e r io d s
*N o te :3 2 o r 6 4 u s
Packet Buffers All data transmission and reception uses the 16 byte packet buffers--one for transmission and one for reception. The transmit buffer allows a complete packet of up to 16 bytes of payload data to be loaded in one burst SPI transaction, and then transmitted with no further MCU intervention. Similarly, the receive buffer allows an entire packet of payload data up to 16 bytes to be received with no firmware intervention required until packet reception is complete. The CYRF6936 IC supports packets up to 255 bytes. However, actual maximum packet length depends on the accuracy of the clock on each end of the link and the data mode; interrupts are provided to allow an MCU to use the transmit and receive buffers as FIFOs. When transmitting a packet longer than 16 bytes, the MCU can load 16 bytes initially, and add further bytes to the transmit buffer as transmission of data creates space in the buffer. Similarly, when receiving packets longer than 16 bytes, the MCU must fetch received data from the FIFO periodically during packet reception to prevent it from overflowing. Auto Transaction Sequencer (ATS) The CYRF6936 IC provides automated support for transmission and reception of acknowledged data packets. When transmitting in transaction mode, the device automatically: * Starts the crystal and synthesizer * Enters transmit mode * Transmits the packet in the transmit buffer * Transitions to receive mode and waits for an ACK packet * Transitions to the transaction end state when either an ACK packet is received, or a timeout period expires Similarly, when receiving in transaction mode, the device automatically: * Waits in receive mode for a valid packet to be received * Transitions to transmit mode, transmits an ACK packet * Transitions to the transaction end state (receive mode to await the next packet, and so on.) The contents of the packet buffers are not affected by the transmission or reception of ACK packets. In each case, the entire packet transaction takes place without any need for MCU firmware action (as long as packets of 16 bytes or less are used); to transmit data the MCU simply must load the data packet to be transmitted, set the length, and set the TX GO bit. Similarly, when receiving packets in transaction mode, firmware simply must retrieve the fully received packet
in response to an interrupt request indicating reception of a packet. Backward Compatibility The CYRF6936 IC is fully interoperable with the main modes of the first generation devices. The 62.5 kbps mode is supported by selecting 32 chip DDR mode. Similarly, the 15.675 kbps mode is supported by selecting 64 chip SDR mode. In this way, a suitably configured CYRF6936 IC device may transmit data to or receive data from a first generation device, or both. Backwards compatibility requires disabling the SOP, length, and CRC16 fields. Data Rates By combining the PN code lengths and data transmission modes described previously, the CYRF6936 IC supports the following data rates: * 1000 kbps (GFSK) * 250 kbps (32 chip 8DR) * 125 kbps (64 chip 8DR) * 62.5 kbps (32 chip DDR) * 31.25 kbps (64 chip DDR) * 15.625 kbps (64 chip SDR)
Functional Block Overview
2.4 GHz Radio The radio transceiver is a dual conversion low IF architecture optimized for power and range/robustness. The radio employs channel-matched filters to achieve high performance in the presence of interference. An integrated Power Amplifier (PA) provides up to +4 dBm transmit power, with an output power control range of 34 dB in seven steps. The supply current of the device is reduced as the RF output power is reduced. Table 1. Internal PA Output Power Step Table PA Setting 7 6 5 4 3 2 1 0 Typical Output Power (dBm) +4 0 -5 -13 -18 -24 -30 -35 Page 4 of 40
Document #: 38-16015 Rev. *G
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CYRF6936
Table 2. Typical Range Observed Table Environment Outdoor Office Home Typical Range (meters) 30 20 15
* Six bits of address. * Eight bits of data. The device receives SCK from an application MCU on the SCK pin. Data from the application MCU is shifted in on the MOSI pin. Data to the application MCU is shifted out on the MISO pin. The active LOW Slave Select (SS) pin must be asserted to initiate an SPI transfer. The application MCU can initiate SPI data transfers using a multi-byte transaction. The first byte is the Command/Address byte, and the following bytes are the data bytes as shown in Figure 4 through Figure 7 on page 6. The SPI communications interface has a burst mechanism, where the first byte can be followed by as many data bytes as desired. A burst transaction is terminated by deasserting the slave select (SS = 1). The SPI communications interface single read and burst read sequences are shown in Figure 5 and Figure 6, respectively. The SPI communications interface single write and burst write sequences are shown in Figure 7 and Figure 8, respectively. This interface may optionally be operated in a 3-pin mode with the MISO and MOSI functions combined in a single bidirectional data pin (SDAT). When using 3-pin mode, user firmware should ensure that the MOSI pin on the MCU is in a high impedance state except when MOSI is actively transmitting data. The device registers may be written to or read from one byte at a time, or several sequential register locations may be written/read in a single SPI transaction using incrementing burst mode. In addition to single byte configuration registers, the device includes register files; register files are FIFOs written to and read from using nonincrementing burst SPI transactions. The IRQ pin function may optionally be multiplexed onto the MOSI pin; when this option is enabled the IRQ function is not available while the SS pin is LOW. When using this configuration, user firmware should ensure that the MOSI pin on the MCU is in a high impedance state whenever the SS pin is HIGH. The SPI interface is not dependent on the internal 12 MHz clock. Registers may therefore be read from or written to while the device is in sleep mode, and the 12 MHz oscillator disabled. The SPI interface and the IRQ and RST pins have a separate voltage reference pin (VIO), enabling the device to interface directly to MCUs operating at voltages below the CYRF6936 IC supply voltage.
Note: Range observed with CY4636 WirelessUSB LP KBM v1.0 (Keyboard)
Frequency Synthesizer Before transmission or reception may begin, the frequency synthesizer must settle. The settling time varies depending on channel; 25 fast channels are provided with a maximum settling time of 100 s. The `fast channels' (less than 100 s settling time) are every third channel, starting at 0 up to and including 72 (for example, 0, 3, 6, 9....69, 72). Baseband and Framer The baseband and framer blocks provide the DSSS encoding and decoding, SOP generation and reception and CRC16 generation and checking, as well as EOP detection and length field. Packet Buffers and Radio Configuration Registers Packet data and configuration registers are accessed through the SPI interface. All configuration registers are directly addressed through the address field in the SPI packet (as in the CYWUSB6934). Configuration registers allow configuration of DSSS PN codes, data rate, operating mode, interrupt masks, interrupt status, and so on. SPI Interface The CYRF6936 IC has an SPI interface supporting communications between an application MCU and one or more slave devices (including the CYRF6936). The SPI interface supports single-byte and multi-byte serial transfers using either 4-pin or 3-pin interfacing. The SPI communications interface consists of Slave Select (SS), Serial Clock (SCK), and Master Out-Slave In (MOSI), Master In-Slave Out (MISO), or Serial Data (SDAT). The SPI communications are as follows: * Command Direction (bit 7) = `1' enables SPI write transaction. A `0' enables SPI read transactions. * Command Increment (bit 6) = `1' enables SPI auto address increment. When set, the address field automatically increments at the end of each data byte in a burst access, otherwise the same address is accessed.
Document #: 38-16015 Rev. *G
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CYRF6936
Figure 4. SPI Transaction Format
Byte 1 Bit # Bit Name 7 DIR 6 INC [5:0] Address Byte 1+N [7:0] Data
Figure 5. SPI Single Read Sequence
SCK SS
cmd addr
A5 A4 A3 A2 A1 A0
MOSI MISO
DIR 0
INC
data to mcu
D7 D6 D5 D4 D3 D2 D1 D0
Figure 6. SPI Incrementing Burst Read Sequence
SCK SS
cmd addr
A5 A4 A3 A2 A1 A0
MOSI MISO
DIR 0
INC
data to mcu1
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6
data to mcu1+N
D5 D4 D3 D2 D1 D0
Figure 7. SPI Single Write Sequence
SCK SS
cmd addr
A5 A4 A3 A2 A1 A0 D7 D6
data from mcu
D5 D4 D3 D2 D1 D0
MOSI MISO
DIR 1
INC
Figure 8. SPI Incrementing Burst Write Sequence
SCK SS
cmd addr
A5 A4 A3 A2 A1 A0 D7 D6
data from mcu1
D5 D4 D3 D2 D1 D0 D7 D6
data from mcu1+N
D5 D4 D3 D2 D1 D0
MOSI MISO
DIR 1
INC
Document #: 38-16015 Rev. *G
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CYRF6936
Interrupts The device provides an interrupt (IRQ) output, which is configurable to indicate the occurrence of various different events. The IRQ pin may be programmed to be either active HIGH or active LOW, and be either a CMOS or open drain output. A full description of all the available interrupts can be found in "Register Descriptions" on page 12. The CYRF6936 IC features three sets of interrupts: transmit, receive, and system interrupts. These interrupts all share a single pin (IRQ), but can be independently enabled/disabled. The contents of the enable registers are preserved when switching between transmit and receive modes. If more than one interrupt is enabled at any time, it is necessary to read the relevant status register to determine which event caused the IRQ pin to assert. Even when a given interrupt source is disabled, the status of the condition that would otherwise cause an interrupt can be determined by reading the appropriate status register. It is therefore possible to use the devices without the IRQ pin by polling the status registers to wait for an event, rather than using the IRQ pin. Clocks A 12 MHz crystal (30 ppm or better) is directly connected between XTAL and GND without the need for external capacitors. A digital clock out function is provided, with selectable output frequencies of 0.75, 1.5, 3, 6, or 12 MHz. This output may be used to clock an external microcontroller (MCU) or ASIC. This output is enabled by default, but may be disabled. Listed below are the requirements for the crystal to be directly connected to XTAL pin and GND. * Nominal Frequency: 12 MHz * Operating Mode: Fundamental Mode * Resonance Mode: Parallel Resonant * Frequency Initial Stability: 30 ppm * Series Resistance: <60 ohms * Load Capacitance: 10 pF * Drive Level: 10 W-100 W Power Management The operating voltage of the device is 1.8V to 3.6V DC, which is applied to the VBAT pin. The device can be shut down to a fully static sleep mode by writing to the FRC END = 1 and END STATE = 000 bits in the XACT_CFG_ADR register over the SPI interface. The device enters sleep mode within 35 s after the last SCK positive edge at the end of this SPI transaction. Alternatively, the device may be configured to automatically enter sleep mode after completing packet transmission or reception. When in sleep mode, the on-chip oscillator is stopped, but the SPI interface remains functional. The device wakes from sleep mode automatically when the device is
commanded to enter transmit or receive mode. When resuming from sleep mode, there is a short delay while the oscillator restarts. The device can be configured to assert the IRQ pin when the oscillator has stabilized. The output voltage (VREG) of the Power Management Unit (PMU) is configurable to several minimum values between 2.4V and 2.7V. VREG may be used to provide up to 15 mA (average load) to external devices. It is possible to disable the PMU, and to provide an externally regulated DC supply voltage to the device's main supply in the range 2.4V to 3.6V. The PMU also provides a regulated 1.8V supply to the logic. The PMU is designed to provide high boost efficiency (74-85% depending on input voltage, output voltage and load) when using a Schottky diode and power inductor, eliminating the need for an external boost converter in many systems where other components require a boosted voltage. However, reasonable efficiencies (69-82% depending on input voltage, output voltage, and load) may be achieved when using low cost components such as SOT23 diodes and 0805 inductors. The PMU also provides a configurable low battery detection function, which may be read over the SPI interface. One of seven thresholds between 1.8V and 2.7V may be selected. The interrupt pin may be configured to assert when the voltage on the VBAT pin falls below the configured threshold. LV IRQ is not a latched event. Battery monitoring is disabled when the device is in sleep mode. Low Noise Amplifier and Received Signal Strength Indication The gain of the receiver can be controlled directly by clearing the AGC EN bit and writing to the Low Noise Amplifier (LNA) bit of the RX_CFG_ADR register. Clearing the LNA bit reduces the receiver gain approximately 20 dB, allowing accurate reception of very strong received signals (for example when operating a receiver very close to the transmitter). Approximately 30 dB of receiver attenuation can be added by setting the Attenuation (ATT) bit; this allows data reception to be limited to devices at very short ranges. Disabling AGC and enabling LNA is recommended unless receiving from a device using external PA. When the device is in receive mode the RSSI_ADR register returns the relative signal strength of the on-channel signal power. When receiving, the device automatically measures and stores the relative strength of the signal being received as a five bit value. An RSSI reading is taken automatically when the SOP is detected. In addition, a new RSSI reading is taken every time the previous reading is read from the RSSI_ADR register, allowing the background RF energy level on any given channel to be easily measured when RSSI is read when no signal is being received. A new reading can occur as fast as once every 12 s.
Document #: 38-16015 Rev. *G
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The power supply decoupling shown for VBAT0 is a recommended cost effective configuration: C6=No Load R2= 1ohm C7=10uF ceramic. For this configuration, it is required that C18 be installed.
VBAT VCC R2
0402
0805
C15
1 1% C7 C16
0402
0805
An alternate decoupling configuration is the following: C6=47uF ceramic R2=0ohm C7=.047uF. For this configuration, it is not required to load C18.
0.047 uFd 10 uFd 6.3V 0.047 uFd R3 C11
Application Examples
Radio Decoupling Caps
For reference design part numbers, please refer to the Bill of Materials file 121-26504_A.xls.
C8
0402
0.047 uFd C10
0402
C13 C19
0402
C20 0.047 uFd C5
0402
0402
0.047 uFd
0402
0.01 uFd
0.01 uFd
27 5
U2 0.47 uFd VBAT
8 6 38
33
40
3 7 16
VDD2 VDD1
BIND
VIO
0402
35
U1 CYRF6936
0402
VBAT2 VBAT1 VBAT0
VREG
S1 RFbias TV8 34 RST RFp RFn RST 10 11 13
C17 0.47 uFd
VCC1 VCC2 VCC3
VDD
1A 2A
1B 2B
L1 22 nH
IND0402
SW PUSHBUTTON
P1_0 P1_1 SW1 nSS SCK MOSI MISO IRQ 25 26 28 29 30 31 32 33 P1_0 P1_1 P1_2 P1_3 / SSEL P1_4 / SCLK P1_5 / SMOSI P1_6 / SMISO P1_7 TV2 TV3 TV4 TV5 24 25 27 28 SS SCK MOSI MISO IRQ 26 TV7 IRQ nSS SCK MOSI MISO PACTL XTAL 30 1 ROW1 ROW2 ROW3 ROW4 ROW5 ROW6 ROW7 ROW8 37 L/D P0_0 / CLKIN P0_1 / CLKOUT P0_2 / INT0 P0_3 / INT1 P0_4 / INT2 P0_5 / TIO0 P0_6 / TIO1 P0_7 23 22 21 20 19 18 17 16 COL1 COL2 COL3 COL4 COL5 COL6 COL7 COL8
L2 1.8 nH C3
0402
15 pFd C4 PACTL TV6 2.0 pFd
0402
0402
COL9 COL10 COL11 COL12 COL13 COL14 COL15 COL16 34 35 36 37 38 39 40 41 P3_0 P3_1 P3_2 P3_3 P3_4 P3_5 P3_6 P3_7 P2_0 P2_1 P2_2 P2_3 P2_4 P2_5 P2_6 P2_7 15 14 13 12 11 10 9 8
1.5 pFd
XOUT
29
CLKOUT TV1
Y1 12 MHz Crystal
J4
COL17 COL18 7 6 42 43 P4_0 P4_1 P4_2 P4_3
Serial debug header
3 2 1
3 PIN HDR
NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 2 4 5 9 14 15 17 18 NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8
1 2 3 4 45 46 47 48
VSS2 VSS1
RESV NC9 NC10 NC11 NC12 NC13 NC14 NC15 NC16
19 20 21 22 23 31 32 36 39
GND1
44 24
CY7C60123-PVXC
12
41
E-PAD
E-PAD must be soldered to ground.
VBAT D1 L3
SOT23
VCC TP1 2 10 uH 1 BAT400D C12
0805
E
+ C18 100 uFd 10v
1210
C6 No Load
VCC
EVCC 10 uFd 6.3V TP2
0603
R1
NO LOAD J2
ISSP
P1_0 P1_1 5 PIN HDR 1 2 3 4 5
J3
1
Figure 9. Recommended Circuit for Systems Where VBAT May Fall Below 2.4V
A 2-pin jumper installed from J3.1 to J2.1 enables the radio to power the processor. Jumper removal is required when programming U2 to disconnect the radio from the Miniprog 5V source. XRES SCLK SDATA
1 PIN HDR
CYRF6936
R1 is a zero ohm resistor that should be installed for production units only, following programming.
Layout J3 and J2.1 in a 0.100" spacing configuration
1 2
Document #: 38-16015 Rev. *G
0.047 uFd C9 1 uFd 6.3V EVCC
RF VCO and VCO Buffer Filter
0402
47
0402
ANT1 WIGGLE 63
IND0603
C1
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CYRF6936
Table 3. Recommended Bill of Materials for Systems Where VBAT May Fall Below 2.4V Item Qty CY Part Number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 1 1 1 1 2 2 1 6 1 1 4 3 1 1 1 1 1 1 1 1 3 1 1 1 1 1 1 1 NA 730-10012 730-11955 730-11398 730R-13322 730-13037 730-13400 730-13404 730-11952 710-13201 730-10794 730-13036 800-13248 420-11964 420-11496 800-13401 800-11651 800-13253 610-13402 620-10539 tmp 630-11356 CYRF6936-40LFC CY7C60323-PVXC 800-13259 PDC-9302-*C 920-11206 920-30200 *C
Reference
ANT1 C1 C3 C4 C5,C17 C12,C7 C8 C9,C10,C11, C13,C15,C16 C19 C18
Description
2.5GHZ H-STUB WIGGLE ANTENNA FOR 63MIL PCB CAP 2.0 PF 50V CERAMIC NPO 0402 CAP 1.5PF 50V CERAMIC NPO 0402 SMD CAP CER 0.47UF 6.3V X5R 0402 NA
Manufacturer
Mfr Part Number
NA ECJ-0EC1H150J C0402C209C5GACTU ECJ-0EC1H1R5C GRM155R60J474KE19D C0805C106K9PACTU ECJ-0EB0J105M 0402YD473KAT2A C0402C104K8PACTU EEU-FC1A101S ECJ-0EB1C103K C0603C105K8PACTU SS12 103185-1 103185-5 ELJ-RE22NGF2 ELJ-RF1N8DF CDH53100LC ERJ-2GEJ470X ERJ-3GEYJ104V 9C06031A5R11FGHFT 9C08052A1R00FKHFT
CAP 15PF 50V CERAMIC NPO 0402 Panasonic Kemet PANASONIC Murata
CAP CERAMIC 10UF 6.3V X5R 0805 Kemet CAP 1 uF 6.3V CERAMIC X5R 0402 Panasonic CAP 0.047 uF 50V CERAMIC X5R 0402 CAP 100UF 10V ELECT FC AVX
CAP 0.1 uF 50V CERAMIC X5R 0402 Kemet Panasonic - ECG Panasonic - ECG
C20,C23,C24,C2 CAP 10000PF 16V CERAMIC 0402 5 SMD C26,C27,C28 D1 J1 J3 L1 L2 L3 R1 R2 R6,R7,R8 R9 U1 U2 Y1 PCB LABEL1 LABEL2 DIODE SCHOTTKY 20V 1A SMA HEADER 1 POS 0.230 HT MODII 0.100CL
CAP CERAMIC 1.0UF 10V X5R 0603 Kemet Taiwan Semiconductor AMP/Tyco
CONN HDR BRKWAY 5POS STR AU AMP Division of TYCO PCB INDUCTOR 22NH 2% FIXED 0603 SMD INDUCTOR 1.8NH +-.3NH FIXED 0402 SMD COIL 10UH 1.23A UNSHIELDED SMD RES 47 OHM 1/16W 5% 0402 SMD RES 100K OHM 1/16W 5% 0603 SMD Panasonic - ECG Panasonic - ECG Sumida Panasonic - ECG Panasonic - ECG
RES CHIP 5.11 OHM 1/16W 1% 0603 Yageo America SMD RES 1.00 OHM 1/8W 1% 0805 SMD Yageo IC WIRELESS MICROCONTROLLER SSOP28 CRYSTAL 12.00MHZ HC49 SMD PRINTED CIRCUIT BOARD Serial Number PCA #
IC, LP 2.4 GHz RADIO SoC QFN-40 Cypress Semiconductor CYRF6936 Rev A5 Cypress Semiconductor CY7C60323-PVXC eCERA GF-1200008
Cypress Semiconductor PDC-9302-*C 121-30200 *C
Document #: 38-16015 Rev. *G
Page 9 of 40
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5V C12 1500 pFd
11
0402
VCC
U2
VCC
5V 0.47 uFd
8 6 38 33 40 3 7 16
J1 10 9 DM/P1_1 DP/P1_0
VIO VBAT2 VBAT1 VBAT0 VREG VCC1 VCC2 VCC3 VDD
IND0603
USB A SMT PLUG RST 34 RST RFp
IND0402
nLED2 nLED1 IRQ SW1 RFbias 22 nH C1 L2 1.8 nH C3 PACTL XTAL 1 30 2.0 pFd
0402
13 14 15 16 SSEL/P1_3 SCLK/P1_4 MOSI/P1_5 MISO/P1_6 RST RFn 13 11
VSS
0402
R1 zero nSS SCK MOSI MISO 24 25 27 28 SS SCK MOSI MISO IRQ 26 IRQ
P0_0 P0_1 P0_2/INT0 P0_3/INT1 P0_4/INT2 P0_5/TIO0 P0_6/TIO1 10 L1
0402
nSS SCK MOSI MISO
7 6 5 4 3 2 1 15 pFd
C4
0402
1.5 pFd
CY7C63803-SXC
8
37 L/D
XOUT
29
TV1
TV-20R
Y1 12 MHz Crystal
5V D1 1 GR RD LED Green Red C 4 nLED2
12
"CONNECT/ACTIVITY"
3 nLED1
2 4 5 9 14 15 17 18 NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8
GND1 E-PAD
RESV NC9 NC10 NC11 NC12 NC13 NC14 NC15 NC16
19 20 21 22 23 31 32 36 39
41
Figure 10. Recommended Circuit for Systems Where VBAT is 2.4V to 3.6V (PMU disabled)
0402
R2 620 C 2
E-PAD must be soldered to ground.
"BIND"
S1 1A 1B SW RA PUSH 2A 2B SW1
VCC
C6
0402
C7 0.047 uFd
0402
C8 0.047 uFd
0402
C9 0.047 uFd
0402
C10 0.047 uFd
0402
C11 0.047 uFd
0402
0.047 uFd
Power Supply
VCC
5V
C13
0805
C14 2.2 uFd
CYRF6936
0805
4.7 uFd
1 2
Document #: 38-16015 Rev. *G
VREG
35
VBUS DM DP GND S1 S2 12
1 2 3 4 5 6
VBUS DM DP U1 CYRF6936
0402
VCC
C5
ANT1 WIGGLE 32
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CYRF6936
Table 4. Recommended Bill of Materials for Systems Where VBAT is 2.4V to 3.6V (PMU disabled) Item Qty
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 1 1 1 1 1 6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CY Part Number
NA 730-10012 730-11955 730-11398 730-13322 730-13404 730-11953 730-13040 730-12003 800-13333 420-13046 800-13401 800-11651 610-10343 610-13472 200-13471 CYRF6936-40LFC CY7C63803-SXC 800-13259 PDC-9263-*B
Reference
ANT1 C1 C3 C4 C5 C6,C7,C8,C9, C10,C11 C12 C13 C14 D1 J1 L1 L2 R1 R2 S1 U1 U2 Y1 PCB LABEL1 LABEL2
Description
2.5GHZ H-STUB WIGGLE ANTENNA FOR 32MIL PCB CAP 2.0 PF 50V CERAMIC NPO 0402 CAP 1.5PF 50V CERAMIC NPO 0402 SMD CAP 0.47 uF 6.3V CERAMIC X5R 0402 CAP 0.047 uF 16V CERAMIC X5R 0402 CAP 1500PF 50V CERAMIC X7R 0402 CAP CERAMIC 4.7UF 6.3V XR5 0805 NA
Manufacturer
Mfr Part Number
NA ECJ-0EC1H150J C0402C209C5GACTU ECJ-0EC1H1R5C GRM155R60J474KE19D 0402YD473KAT2A C0402C152K5RACTU C0805C475K9PACTU GRM21BR71A225KA01L LTST-C155KGJRKT UAR72-4N5J10 ELJ-RE22NGF2 ELJ-RF1N8DF ERJ-2GE0R00X ERJ-2GEJ621X EVQ-P7J01K
CAP 15PF 50V CERAMIC NPO 0402 Panasonic Kemet PANASONIC Murata AVX Kemet Kemet
CAP CER 2.2UF 10V 10% X7R 0805 Murata Electronics North America LED GREEN/RED BICOLOR 1210 SMD INDUCTOR 22NH 2% FIXED 0603 SMD INDUCTOR 1.8NH +-.3NH FIXED 0402 SMD LITEON
CONN USB PLUG TYPE A PCB SMT ACON Panasonic - ECG Panasonic - ECG
RES ZERO OHM 1/16W 0402 SMD Panasonic - ECG RES CHIP 620 OHM 1/16W 5% 0402 Panasonic - ECG SMD SWITCH LT 3.5MMX2.9MM 160GF SMD IC LOW-SPEED USB ENCORE II CONTROLLER SOIC16 CRYSTAL 12.00MHZ HC49 SMD PRINTED CIRCUIT BOARD Serial Number PCA # Panasonic - ECG
IC, LP 2.4 GHz RADIO SoC QFN-40 Cypress Semiconductor CYRF6936 Rev A5 Cypress Semiconductor CY7C63803-SXC eCERA XXXXXX 121-26305 ** GF-1200008
Cypress Semiconductor PDC-9263-*B
Document #: 38-16015 Rev. *G
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CYRF6936
Register Descriptions
All registers are read and writable, except where noted. Registers may be written to or read from either individually or in sequential groups. Table 5. Register Map Summary
Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 Mnemonic CHANNEL_ADR TX_LENGTH_ADR TX_CTRL_ADR TX_CFG_ADR TX_IRQ_STATUS_ADR RX_CTRL_ADR RX_CFG_ADR 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x26 0x27 0x28 0x29 0x32 0x35 0x39 RX_IRQ_STATUS_ADR RX_STATUS_ADR RX_COUNT_ADR RX_LENGTH_ADR PWR_CTRL_ADR XTAL_CTRL_ADR IO_CFG_ADR GPIO_CTRL_ADR XACT_CFG_ADR FRAMING_CFG_ADR DATA32_THOLD_ADR DATA64_THOLD_ADR RSSI_ADR EOP_CTRL_ADR CRC_SEED_LSB_ADR CRC_SEED_MSB_ADR TX_CRC_LSB_ADR TX_CRC_MSB_ADR RX_CRC_LSB_ADR RX_CRC_MSB_ADR TX_OFFSET_LSB_ADR TX_OFFSET_MSB_ADR MODE_OVERRIDE_ADR RX_OVERRIDE_ADR TX_OVERRIDE_ADR XTAL_CFG_ADR CLK_OVERRIDE_ADR CLK_EN_ADR RX_ABORT_ADR AUTO_CAL_TIME_ADR AUTO_CAL_OFFSET_ADR ANALOG_CTRL_ADR RSVD RSVD RSVD b7 Not Used b6 b5 b3 Channel TX Length TXB8 TXB0 IRQEN IRQEN b4 b2 b1 b0 Default[1] -1001000 00000000 00000011 --000101 DATA MODE TXB8 TXB0 TXBERR IRQ IRQ IRQ RXB8 RXB1 RXBERR IRQEN IRQEN IRQEN FAST TURN HILO EN Not Used RXB8 RXB1 RXBERR IRQ IRQ IRQ CRC0 Bad CRC RX Code RX Count RX Length Not Used LVI TH Not Used XOUT OD IRQ OP PA SETTING TXC IRQ RXC IRQEN TXE IRQ RXE IRQEN -------00000111 10010-10 RXOW EN VLD EN RXC RXE IRQ IRQ RX Data Mode --------------00000000 00000000 10100000 000--100 00000000 0000---1-000000 10100101 ----0100 ---01010 0-100000 10100100 00000000 00000000 --------------11111111 11111111 00000000 ----0000 00000--0 000000000000000 00000000 00000000 00000000 00000000 00000011 00000000 RSVD RX INV ALL SLOW 00000000 Access[1] -bbbbbbb bbbbbbbb bbbbbbbb --bbbbbb rrrrrrrr bbbbbbbb bbbbb-bb brrrrrrr rrrrrrrr rrrrrrrr rrrrrrrr bbb-bbbb bbb--bbb bbbbbbbb bbbbrrrr b-bbbbbb bbbbbbbb ----bbbb ---bbbbb r-rrrrrr bbbbbbbb bbbbbbbb bbbbbbbb rrrrrrrr rrrrrrrr rrrrrrrr rrrrrrrr bbbbbbbb ----bbbb wwwww--w bbbbbbbbbbbbbbb wwwwwww w wwwwwww w wwwwwww w wwwwwww w wwwwwww w wwwwwww w wwwwwww w wwwwwww w rrrrrrrr bbbbbbbb bbbbbbbb bbbbbbbb rrrrrrrr
TX GO Not Used OS IRQ RX GO AGC EN RXOW IRQ RX ACK
TX CLR Not Used LV IRQ RSVD LNA SOPDET IRQ PKT ERR
TXB15 IRQEN DATA CODE LENGTH TXB15 IRQ RXB16 IRQEN ATT RXB16 IRQ EOP ERR
TXBERR IRQEN
TXC IRQEN
TXE IRQEN
PMU EN
LVIRQ EN
XOUT FN IRQ OD IRQ POL XOUT OP MISO OP ACK EN Not Used SOP EN SOP LEN Not Used Not Used Not Used Not Used SOP Not Used HEN
PMU Mode Force XSIRQ EN MISO OD PACTL OP FRC END LEN EN Not Used Not Used LNA HINT
PMU OUTV
Not Used RSVD ACK RX ACK TX RSVD RSVD RSVD RSVD
Not Used RSVD RXTX DLY FRC PRE RSVD RSVD RSVD RSVD
Not Used FRC SEN MAN RXACK RSVD RSVD RSVD RSVD ABORT EN
Not Used FREQ PACTL OD PACTL GPIO SPI 3PIN IRQ GPIO XOUT IP MISO IP PACTL IP IRQ IP END STATE ACK TO SOP TH Not Used TH32 TH64 RSSI EOP CRC SEED LSB CRC SEED MSB CRC LSB CRC MSB CRC LSB CRC MSB STRIM LSB Not Used STRIM MSB FRC AWAKE Not Used Not Used RST FRC RXDR DIS CRC0 DIS RXCRC ACE Not Used MAN TXACK OVRD ACK DIS TXCRC RSVD TX INV RSVD START DLY RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RXF RXF RSVD RSVD RSVD RSVD
AUTO_CAL_TIME AUTO_CAL_OFFSET RSVD RSVD
Register Files 0x20 TX_BUFFER_ADR 0x21 0x22 0x23 0x24 0x25 RX_BUFFER_ADR SOP_CODE_ADR DATA_CODE_ADR PREAMBLE_ADR MFG_ID_ADR
TX Buffer File RX Buffer File SOP Code File Data Code File Preamble File MFG ID File
--------------Note 2 Note 3 Note 4 NA
Notes 1. b = read/write; r = read only; w = write only; `-' = not used, default value is undefined. 2. SOP_CODE_ADR default = 0x17FF9E213690C782. 3. DATA_CODE_ADR default = 0x02F9939702FA5CE3012BF1DB0132BE6F. 4. PREAMBLE_ADR default = 0x333302.
Document #: 38-16015 Rev. *G
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CYRF6936
Mnemonic Bit Default Read/Write Function Bit 7 Bits 6:0 7 Not Used 6 1 R/W
CHANNEL_ADR 5 0 R/W 4 0 R/W 3 1 R/W Channel 2 0 R/W
Address 1 0 R/W 0 0
0x00
R/W
Not Used. This field selects the channel. 0x00 sets 2400 MHz; 0x62 sets 2498 MHz. Values above 0x62 are not valid. The default channel is a fast channel above the frequency typically used in non-overlapping WiFi systems. Any write to this register impacts the time it takes the synthesizer to settle. fast (100 s) - 0 3 6 9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 63 66 69 72 96 medium (180 s) - 2 4 8 10 14 16 20 22 26 28 32 34 38 40 44 46 50 52 56 58 62 64 68 70 74 76 78 80 82 84 86 88 90 92 94 slow (270 s) - 1 5 7 11 13 17 19 23 25 29 31 35 35 37 41 43 47 49 53 55 59 61 65 67 71 73 75 77 79 81 83 85 87 89 91 93 95 97 Usable channels subject to regulation. Do not access or modify this register during Transmit or Receive.
Mnemonic Bit Default Read/Write Function Bits 7:0 7 0 R/W 6 0 R/W
TX_LENGTH_ADR 5 0 R/W 4 0 R/W TX Length 3 0 R/W 2 0 R/W
Address 1 0 R/W 0 0
0x01
R/W
This register sets the length of the packet to be transmitted. A length of zero is valid, and transmits a packet with SOP, length and CRC16 fields (if enabled), but no data field. Packet lengths of more than 16 bytes require that some data bytes be written after transmission of the packet has begun. Typically, length is updated prior to setting TX GO. The maximum packet length for all packets is 40 bytes except for framed 64 chip DDR where the maximum packet length is 16 bytes.
Maximum packet length is limited by the delta between the transmitter and receiver crystals of 60 ppm or better.
Mnemonic Bit Default Read/Write Function TX GO Bit 7 TX CLR 7 0 R/W 6 0 R/W
TX_CTRL_ADR 5 0 R/W TXB15 IRQEN 4 0 R/W TXB8 IRQEN 3 0 R/W TXB0 IRQEN 2 0 R/W TXBERR IRQEN
Address 1 1 R/W TXC IRQEN 0 1
0x02
R/W TXE IRQEN
Start Transmission. Setting this bit triggers the transmission of a packet. Writing `0' to this flag has no effect. This bit is cleared automatically at the end of packet transmission. The transmit buffer may be loaded either before or after setting this bit. If data is loaded after setting this bit, the length of time available to load the buffer depends on the starting state (sleep, idle or synth), the length of the SOP code, the length of preamble, and the packet data rate. For example, if starting from idle mode on a fast channel in 8DR mode with 32 chip SOP codes the time available is 100 s (synth start) + 32 s (preamble) + 64 s (SOP length) + 32 s (length byte) = 228 s. If there are no bytes in the TX buffer at the end of transmission of the length field, a TXBERR IRQ occurs. Clear TX Buffer. Writing `1' to this register clears the transmit buffer. Writing `0' to this bit has no effect. The previous packet (16 or fewer bytes) may be retransmitted by setting TX GO and not setting this bit. Buffer Not Full Interrupt Enable. See TX_IRQ_STATUS_ADR for description. Buffer Half Empty Interrupt Enable. See TX_IRQ_STATUS_ADR for description. Buffer Empty Interrupt Enable. See TX_IRQ_STATUS_ADR for description. Buffer Error Interrupt Enable. See TX_IRQ_STATUS_ADR for description. Transmission Complete Interrupt Enable. TXC IRQEN and TXE IRQEN must be set together. See TX_IRQ_STATUS_ADR for description. Transmit Error Interrupt Enable. TXC IRQEN and TXE IRQEN must be set together. See TX_IRQ_STATUS_ADR for description.
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Document #: 38-16015 Rev. *G
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CYRF6936
Mnemonic Bit Default Read/Write Function Not Used Bit 5 Bits 4:3 Bits 2:0 Not Used 7 6 -
TX_CFG_ADR 5 0 R/W Data Code Length 4 0 R/W Data Mode 3 0 R/W 2 1 R/W
Address 1 0 R/W PA Setting 0 1
0x03
R/W
Data Code Length. This bit selects the length of the DATA_CODE_ADR code for the data portion of the packet. This bit is ignored when the data mode is set to GFSK. 1 = 64 chip codes. 0 = 32 chip codes. Data Mode. This field sets the data transmission mode. 00 = 1-Mbps GFSK. 01 = 8DR Mode. 10 = DDR Mode. 11 = SDR Mode. It is recommended that firmware set the ALL SLOW bit in register ANALOG_CTRL_ADR when using GFSK data rate mode. PA Setting. This field sets the transmit signal strength. 0 = -35 dBm, 1 = -30 dBm, 2 = -24 dBm, 3 = -18 dBm, 4 = -13 dBm, 5 = -5 dBm, 6 = 0 dBm, 7 = +4 dBm.
Mnemonic Bit Default Read/Write Function 7 R OS IRQ
TX_IRQ_STATUS_ADR 6 R LV IRQ 5 R TXB15 IRQ 4 R TXB8 IRQ 3 R TXB0 IRQ 2 R TXBERR IRQ
Address 1 R TXC IRQ 0 R
0x04
TXE IRQ
The state of all IRQ status bits is valid regardless of whether or not the IRQ is enabled. The IRQ output of the device is in its active state whenever one or more bits in this register is set and the corresponding IRQ enable bit is also set. Status bits are non-atomic (different flags may change value at different times in response to a single event). Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Oscillator Stable IRQ Status. This bit is set when the internal crystal oscillator has settled (synthesizer sequence starts). Low Voltage Interrupt Status. This bit is set when the voltage on VBAT is below the LVI threshold (see PWR_CTL_ADR). This interrupt is automatically disabled whenever the PMU is disabled. When enabled, this bit reflects the voltage on VBAT. Buffer Not Full Interrupt Status. This bit is set whenever there are 15 or fewer bytes remaining in the transmit buffer. Buffer Half Empty Interrupt Status. This bit is set whenever there are eight or fewer bytes remaining in the transmit buffer. Buffer Empty Interrupt Status. This bit is set at any time that the transmit buffer is empty. Buffer Error Interrupt Status. This IRQ is triggered by either of two events: (1) When the transmit buffer (TX_BUFFER_ADR) is empty and the number of bytes remaining to be transmitted is greater than zero. (2) When a byte is written to the transmit buffer and the buffer is already full. This IRQ is cleared by setting bit TX CLR in TX_CTRL_ADR. Transmission Complete Interrupt Status. This IRQ is triggered when transmission is complete. If transaction mode is not enabled then this interrupt is triggered immediately after transmission of the last bit of the CRC16. If transaction mode is enabled, this interrupt is triggered at the end of a transaction. Reading this register clears this bit. TXC IRQ and TXE IRQ flags may change value at different times in response to a single event. If transaction mode is enabled and the first read of this register returns TXC IRQ = 1 and TXE IRQ = 0 then firmware must execute a second read to this register to determine if an error occurred by examining the status of TXE. There can be a case when this bit is not triggered when ACK EN = 1 and there is an error in transmission. If the first read of this register returns TXC IRQ = 1 and TXE IRQ = 1, then the firmware must not execute a second read from this register for a given transaction. If an ACK is received RXC IRQ and RXE IRQ may be asserted instead of TXC IRQ and TXE IRQ. Transmit Error Interrupt Status. This IRQ is triggered when there is an error in transmission. This interrupt is only applicable to transaction mode. It is triggered whenever no valid ACK packet is received within the ACK timeout period. Reading this register clears this bit. See TXC IRQ, above.
Bit 1
Bit 0
Document #: 38-16015 Rev. *G
Page 14 of 40
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CYRF6936
Mnemonic Bit Default Read/Write Function RX GO Bit 7 RSVD 7 0 R/W 6 0 R/W
RX_CTRL_ADR 5 0 R/W RXB16 IRQEN 4 0 R/W RXB8 IRQEN 3 0 R/W RXB1 IRQEN 2 1 R/W RXBERR IRQEN
Address 1 1 R/W RXC IRQEN 0 1
0x05
R/W RXE IRQEN
Start Receive. Setting this bit causes the device to transition to receive mode. If necessary, the crystal oscillator and synthesizer start automatically after this bit is set. Firmware must never clear this bit. This bit must not be set again until after it clears. The recommended method to exit receive mode when an error has occurred is to force END STATE and then dummy read all RX_COUNT_ADR bytes from RX_BUFFER_ADR or poll RSSI_ADR.SOP (bit 7) until set. See XACT_CFG_ADR and RX_ABORT_ADR for description. Reserved. Must be zero. Buffer Full Interrupt Enable. See RX_IRQ_STATUS_ADR for description. Buffer Half Empty Interrupt Enable. See RX_IRQ_STATUS_ADR for description. Buffer Not Empty Interrupt Enable. RXB1 IRQEN must not be set when RXB8 IRQEN is set and vice versa. See RX_IRQ_STATUS_ADR for description. Buffer Error Interrupt Enable. See RX_IRQ_STATUS_ADR for description. Packet Reception Complete Interrupt Enable. See RX_IRQ_STATUS_ADR for description. Receive Error Interrupt Enable. See RX_IRQ_STATUS_ADR for description.
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Document #: 38-16015 Rev. *G
Page 15 of 40
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CYRF6936
Mnemonic Bit Default Read/Write Function 7 1 R/W AGC EN 6 0 R/W LNA
RX_CFG_ADR 5 0 R/W ATT 4 1 R/W HILO 3 0 R/W FAST TURN EN 2 Not Used
Address 1 1 R/W RXOW EN 0 0
0x06
R/W VLD EN
Status bits are non-atomic (different flags may change value at different times in response to a single event). Bit 7 Automatic Gain Control (AGC) Enable. When this bit is set, AGC is enabled, and the LNA is controlled by the AGC circuit. When this bit is cleared the LNA is controlled manually using the LNA bit. Typical applications clear this bit during initialization. It is recommended that this bit be cleared and bit 6 (LNA) be set unless the device is used in a system where it may receive data from a device using an external PA to transmit signals at more than +4 dBm. Low Noise Amplifier (LNA) Manual Control. When AGC EN (Bit 7) is cleared, this bit controls the state of the receiver LNA; when AGC EN is set, this bit has no effect. Setting this bit enables the LNA; clearing this bit disables the LNA. Device current in receive mode is slightly lower when the LNA is disabled. Typical applications set this bit during initialization. Receive Attenuator Enable. Setting this bit enables the receiver attenuator. The receiver attenuator may be used to desensitize the receiver so that only very strong signals may be received. This bit should only be set when the AGC EN is disabled and the LNA is manually disabled. HILO. When FAST TURN EN is set, this bit is used to select whether the device uses the high frequency for the channel selected, or the low frequency. 1 = hi; 0 = lo. When FAST TURN EN is not enabled this also controls the high-low bit to the receiver and should be left at the default value of `1' for high side receive injection. Typical applications clear this bit during initialization. Fast Turn Mode Enable. When this bit is set, the HILO bit determines whether the device receives data transmitted 1 MHz above the RX Synthesizer frequency or 1 MHz below the receiver synthesizer frequency. Use of this mode allows for very fast turnaround, because the same synthesizer frequency may be used for both transmit and receive, thus eliminating the synthesizer resettling period between transmit and receive. Note that when this bit is set, and the HILO bit is cleared, received data bits are automatically inverted to compensate for the inversion of data received on the `image' frequency. Typical applications set this bit during initialization. Overwrite Enable. When this bit is set, if an SOP is detected while the receive buffer is not empty, then the existing contents of receive buffer are lost, and the new packet is loaded into the receive buffer. When this bit is set, the RXOW IRQ is enabled. If this bit is cleared, then the receive buffer may not be overwritten by a new packet, and whenever the receive buffer is not empty SOP conditions are ignored, and it is not possible to receive data until the previously received packet has been completely read from the receive buffer. Valid Flag Enable. When this bit is set, the receive buffer can store up to eight bytes of data. Typically, this bit is set only when interoperability with first generation devices is desired. See RX_BUFFER_ADR for more detail.
Bit 6
Bit 5
Bit 4
Bit 3
Bit 1
Bit 0
Document #: 38-16015 Rev. *G
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CYRF6936
Mnemonic Bit Default Read/Write Function 7 R/W RXOW IRQ
RX_IRQ_STATUS_ADR 6 R SOPDET IRQ 5 R RXB16 IRQ 4 R RXB8 IRQ 3 R RXB1 IRQ 2 R RXBERR IRQ
Address 1 R RXC IRQ 0 R
0x07
RXE IRQ
The state of all IRQ Status bits is valid regardless of whether or not the IRQ is enabled. The IRQ output of the device is in its active state whenever one or more bits in this register is set and the corresponding IRQ enable bit is also set. Status bits are non-atomic (different flags may change value at different times in response to a single event). Bit 7 Receive Overwrite Interrupt Status. This IRQ is triggered when the receive buffer is overwritten by a packet being received before the previous packet has been read from the buffer. This bit is cleared by writing any value to this register. This condition is only possible when the RXOW EN bit in RX_CFG_ADR is set. This bit must be written `1' by firmware before the new packet may be read from the receive buffer. Start of packet detect. This bit is set whenever the start of packet symbol is detected. Receive Buffer Full Interrupt Status. This bit is set whenever the receive buffer is full, and cleared otherwise. Receive Buffer Half Full Interrupt Status. This bit is set whenever there are eight or more bytes remaining in the receive buffer. Firmware must read exactly eight bytes when reading RXB8 IRQ. Receive Buffer Not Empty Interrupt Status. This bit is set any time that there are one or more bytes in the receive buffer, and cleared when the receive buffer is empty. It is possible, in rare cases, that the last byte of a packet may remain in the buffer even though the RXB1 IRQ flag has cleared. This can ONLY happen on the last byte of a packet and only if the packet data is being read out of the buffer while the packet is still being received. The flag is trustworthy under all other conditions, and for all bytes prior to the last. When using RXB1 IRQ and unloading the packet data during reception, the user must make sure the RX_COUNT_ADR value, after the RXC IRQ/RXE IRQ, is set and unload the last remaining bytes if the number of bytes unloaded is less than the reported count, even though the RXB1 IRQ is not set. Receive Buffer Error Interrupt Status. This IRQ is triggered in one of two ways: (1) When the receive buffer is empty and there is an attempt to read data (2) When the receive buffer is full and more data is received; this flag is cleared when RX GO is set and a SOP is received. Packet Receive Complete Interrupt Status. This IRQ is triggered when a packet has been received. If transaction mode is enabled, then this bit is not set until after transmission of the ACK. If transaction mode is not enabled then this bit is set as soon as a valid packet is received. This bit is cleared when this register is read. RXC IRQ and RXE IRQ flags may change value at different times in response to a single event. There are cases when this bit is not triggered when ACK EN = 1 and there is an error in reception. Therefore, firmware should examine RXC IRQ, RXE IRQ, and CRC 0 to determine receive status. If the first read of this register returns RXC IRQ = 1 and RXE IRQ = 0 then firmware must execute a second read to this register to determine if an error occurred by examining the status of RXE IRQ. If the first read of this register returns RXC IRQ = 1 and RXE IRQ = 1, then the firmware must not execute a second read to this register for a given transaction. Receive Error Interrupt Status. This IRQ is triggered when there is an error in reception. It is triggered whenever a packet is received with a bad CRC16, an unexpected EOP is detected, a packet type (data or ACK) mismatch, or a packet is dropped because the receive buffer is still not empty when the next packet starts. The exact cause of the error may be determined by reading RX_STATUS_ADR. This bit is cleared when this register is read.
Bit 6 Bit 5 Bit 4 Bit 3
Bit 2
Bit 1
Bit 0
Document #: 38-16015 Rev. *G
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CYRF6936
Mnemonic Bit Default Read/Write Function 7 R RX ACK 6 R
RX_STATUS_ADR 5 R EOP ERR 4 R CRC0 3 R Bad CRC 2 R RX Code
Address 1 R 0 R
0x08
PKT ERR
RX Data Mode
It is expected that firmware does not read this register until after RX GO self clears. Status bits are non-atomic (different flags may change value at different times in response to a single event). Bit 7 RX Packet Type. This bit is set when the received packet is an ACK packet, and cleared when the received packet is a standard packet. Bit 6 Bit 5 Receive Packet Type Error. This bit is set when the packet type received is not what was expected and cleared when the packet type received was as expected. For example, if a data packet is expected and an ACK is received, this bit is set. Unexpected EOP. This bit is set when an EOP is detected before the expected data length and CRC16 fields have been received. This bit is cleared when an SOP pattern for the next packet has been received. This includes the case where there are invalid bits detected in the length field and the length field is forced to `0'. Zero-seed CRC16. This bit is set whenever the CRC16 of the last received packet has a zero seed. Bad CRC16. This bit is set when the CRC16 of the last received packet is incorrect. Receive Code Length. This bit indicates the DATA_CODE_ADR code length used in the last correctly received packet. 1 = 64 chip code, 0 = 32 chip code. Receive Data Mode. These bits indicate the data mode of the last correctly received packet. 00 = 1 Mbps GFSK; 01 = 8DR; 10 = DDR; 11 = Not Valid. These bits do not apply to unframed packets.
Bit 4 Bit 3 Bit 2 Bits 1:0
Mnemonic Bit Default Read/Write Function 7 0 R 6 0 R
RX_COUNT_ADR 5 0 R 4 0 R RX Count 3 0 R 2 0 R
Address 1 0 R 0 0 R
0x09
Count bits are non-atomic (updated at different times). Bits 7:0 This register contains the total number of payload bytes received during reception of the current packet. After packet reception is complete, this register matches the value in RX_LENGTH_ADR unless there was a packet error. This register is cleared when RX_LENGTH_ADR is automatically loaded, if length is enabled, after the SOP. Count should not be read when RX_GO = 1 during a transaction.
Mnemonic Bit Default Read/Write Function 7 0 R 6 0 R
RX_LENGTH_ADR 5 0 R 4 0 R RX Length 3 0 R 2 0 R
Address 1 0 R 0 0 R
0x0A
Length bits are non-atomic (different flags may change value at different times in response to a single event). Bits 7:0 This register contains the length field which is updated with the reception of a new length field (shortly after start of packet detected). If there is an error in the received length field, 0x00 is loaded instead, except when using GFSK data rate, and an error is flagged.
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Mnemonic Bit Default Read/Write Function Bit 7 Bit 6 7 1 R/W PMU EN 6 0 R/W
PWR_CTRL_ADR 5 1 R/W PMU Mode Force 4 PFET Disable 3 0 R/W LVI TH 2 0 R/W
Address 1 0 R/W 0 0
0x0B
R/W
LVIRQ EN
PMU OUTV
Power Management Unit (PMU) Enable. Setting this bit enables the PMU only if PMU Mode Force (bit 5) is set. Otherwise it has no effect. See PMU Mode Force (bit 5) description for more information. Low Voltage Interrupt Enable. Setting this bit enables the LV IRQ interrupt. When this interrupt is enabled, if the VBAT voltage falls below the threshold set by LVI TH, a low voltage interrupt is generated. The LVI is not available when the device is in sleep mode. The LVI event on IRQ pin is automatically disabled whenever the PMU is disabled. PMU Mode Force. If this bit is set, the PMU operation is based on the state of the PMU Enable Bit (bit 7). if this bit is not set then the PMU is disabled in Sleep mode and enabled when not in Sleep mode, if Bit 7 = 1. If Bit 7 = 1 and Bit 5 = 1, PMU is enabled always (even during sleep). If Bit 7 = 0 and Bit 5 = 1, PMU is disabled always. If Bit 7 = 1and Bit 5 = 0, PMU is disabled only in Sleep Mode. Low Voltage Interrupt Threshold. This field sets the voltage on VBAT at which the LVI is triggered. 11 = 1.8V; 10 = 2.0V; 01 = 2.2V; 00 = PMU OUTV voltage. PMU Output Voltage. This field sets the minimum output voltage of the PMU. 11 = 2.4V; 10 = 2.5V; 01 = 2.6V; 00 = 2.7V. When the PMU is active, the voltage output by the PMU on VREG is never less than this voltage, provided that the total load on the VREG pin is less than the specified maximum value, and the voltage in VBAT is greater than the specified minimum value.
Bit 5
Bits 3:2 Bits 1:0
The order of writing these bits impacts the value of the Sleep current ISB.
Mnemonic Bit Default Read/Write Function Bits 7:6 7 0 R/W XOUT FN 6 0 R/W
XTAL_CTRL_ADR 5 0 R/W XSIRQ EN 4 Not Used 3 Not Used 2 1 R/W
Address 1 0 R/W FREQ 0 0
0x0C
R/W
XOUT Pin Function. This field selects between the different functions of the XOUT pin. 00 = Clock frequency set by XOUT FREQ; 01 = Active LOW PA Control; 10 = Radio data serial bit stream. If this option is selected and SPI is configured for 3-wire mode then the MISO pin outputs a serial clock associated with this data stream; 11 = GPIO. To disable this output, set to GPIO mode, and set the GPIO state in IO_CFG_ADR. Crystal Stable Interrupt Enable. This bit enables the OS IRQ interrupt. When enabled, this interrupt generates an IRQ event when the crystal has stabilized after the device has awaken from sleep mode. This event is cleared by writing `0' to this bit. XOUT Frequency. This field sets the frequency output on the XOUT pin when XOUT FN is set to 00. 0 = 12 MHz; 1 = 6 MHz, 2 = 3 MHz, 3 = 1.5 MHz, 4 = 0.75 MHz; other values are not defined.
Bit 5 Bits 2:0
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Mnemonic Bit Default Read/Write Function 7 0 R/W IRQ OD 6 0 R/W IRQ POL
IO_CFG_ADR 5 0 R/W MISO OD 4 0 R/W XOUT OD 3 0 R/W PACTL OD 2 0 R/W PACTL GPIO
Address 1 0 R/W SPI 3PIN 0 0
0x0D
R/W IRQ GPIO
To use a GPIO pin as an input, the output mode must be set to open drain, and `1' written to the corresponding output register bit. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 IRQ Pin Drive Strength. Setting this bit configures the IRQ pin as an open drain output. Clearing this bit configures the IRQ pin as a standard CMOS output, with the output `1' drive voltage being equal to the VIO pin voltage. IRQ Polarity. Setting this bit configures the IRQ signal polarity to be active HIGH. Clearing this bit configures the IRQ signal polarity to be active low. MISO Pin Drive Strength. Setting this bit configures the MISO pin as an open drain output. Clearing this bit configures the MISO pin as a standard CMOS output, with the output `1' drive voltage being equal to the VIO pin voltage. XOUT Pin Drive Strength. Setting this bit configures the XOUT pin as an open drain output. Clearing this bit configures the XOUT pin as a standard CMOS output, with the output `1' drive voltage being equal to the VIO pin voltage. PACTL Pin Drive Strength. Setting this bit configures the PACTL pin as an open drain output. Clearing this bit configures the PACTL pin as a standard CMOS output, with the output `1' drive voltage being equal to the VIO pin voltage. PACTL Pin Function. When this bit is set, the PACTL pin is available for use as a GPIO. SPI Mode. When this bit is cleared, the SPI interface acts as a standard 4-wire SPI Slave interface. When this bit is set, the SPI interface operates in "3-Wire Mode" combining MISO and MOSI on the same pin (SDAT). The MISO pin is available as a GPIO pin. IRQ Pin Function. When this bit is cleared, the IRQ pin is asserted when an IRQ is active; the polarity of this IRQ signal is configurable in IRQ POL. When this bit is set, the IRQ pin is available for use as a GPIO pin, and the IRQ function is multiplexed onto the MOSI pin. In this case the IRQ signal state is presented on the MOSI pin whenever the SS signal is inactive (HIGH).
Bit 0
Mnemonic Bit Default Read/Write Function 7 0 R/W XOUT OP 6 0 R/W
GPIO_CTRL_ADR 5 0 R/W PACTL OP 4 0 R/W IRQ OP 3 R XOUT IP 2 R MISO IP
Address 1 R PACTL IP 0 R
0x0E
MISO OP
IRQ IP
To use a GPIO pin as an input, the output mode must be set to open drain, and a `1' written to the corresponding output register bit. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 XOUT Output. When the XOUT pin is configured to be a GPIO, the state of this bit sets the output state of the XOUT pin. MISO Output. When the MISO pin is configured to be a GPIO, the state of this bit sets the output state of the MISO pin. PACTL Output. When the PACTL pin is configured to be a GPIO, the state of this bit sets the output state of the PACTL pin. IRQ Output. When the IRQ pin is configured to be a GPIO, the state of this bit sets the output state of the IRQ pin. XOUT Input. The state of this bit reflects the voltage on the XOUT pin. MISO Input. The state of this bit reflects the voltage on the MISO pin. PACTL Input. The state of this bit reflects the voltage on the PACTL pin. IRQ Input. The state of this bit reflects the voltage on the IRQ pin.
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Mnemonic Bit Default Read/Write Function Bit 7 7 1 R/W ACK EN 6 -
XACT_CFG_ADR 5 0 R/W FRC END 4 0 R/W 3 0 R/W END STATE 2 0 R/W
Address 1 0 R/W ACK TO 0 0
0x0F
R/W
Not Used
Acknowledge Enable. When this bit is set, an ACK packet is automatically transmitted whenever a valid packet is received; in this case the device is considered to be in transaction mode. After transmission of the ACK packet, the device automatically transitions to the END STATE. When this bit is cleared, the device transitions directly to the END STATE immediately after the end of packet transmission. This bit affects both transmitting and receiving devices. Force End State. Setting this bit forces a transition to the state set in END STATE. By setting the desired END STATE at the same time as setting this bit the device may be forced to immediately transition from its current state to any other state. This bit is automatically cleared upon completion. Firmware MUST never try to force END STATE while TX GO is set, nor when RX GO is set and a SOP has already been received (packet reception already in progress). Transaction End State. This field defines the mode to which the device transitions after receiving or transmitting a packet. 000 = Sleep Mode; 001 = Idle Mode; 010 = Synth Mode (TX); 011 = Synth Mode (RX); 100 = RX Mode. In normal use, this field is typically set to `000' or `001' when the device is transmitting packets, and `100' when the device is receiving packets. Note that when the device transitions to receive mode as an END STATE, the receiver must still be armed by setting RX GO before the device can begin receiving data. If the system only supports packets less than or equal to 16 bytes then firmware should examine RXC IRQ and RXE IRQ to determine the status of the packet. If the system supports packets more than 16 bytes, make sure that END STATE is not sleep, force RXF = 1, perform receive operation, force RXF = 0, and if necessary set END STATE back to sleep. ACK Timeout. When the device is configured for transaction mode, this field sets the timeout period after transmission of a packet during which an ACK must be correctly received in order to prevent a transmit error condition from being detected. This timeout period is expressed in terms of a number of SOP_CODE_ADR code lengths; if SOP LEN is set, then the timeout period is this value multiplied by 64 s and if SOP LEN is cleared then the timeout is this value multiplied by 32 s. 00 = 4x; 01 = 8x, 10 = 12x; 11 = 15x the SOP_CODE_ADR code length. ACK_TO must be set to greater than 30 + Data Code Length (only for 8DR) + Preamble Length + SOP Code Length (x2).
Bit 5
Bits 4:2
Bits 1:0
Mnemonic Bit Default Read/Write Function Bit 7 7 1 R/W SOP EN
FRAMING_CFG_ADR 6 0 R/W SOP LEN 5 1 R/W LEN EN 4 0 R/W 3 0 R/W 2 1 R/W SOP TH
Address 1 0 R/W 0 1
0x10
R/W
SOP Enable. When this bit is set, each transmitted packet begins with a SOP field, and only packets beginning with a valid SOP field are received. If this bit is cleared, no SOP field is generated when a packet is transmitted, and packet reception begins whenever two successive correlations against the DATA_CODE_ADR code are detected. SOP PN Code Length. When this bit is set the SOP_CODE_ADR code length is 64 chips. When this bit is cleared the SOP_CODE_ADR code length is 32 chips. Packet Length Enable. When this bit is set the 8 bit value contained in TX_LENGTH_ADR is transmitted immediately after the SOP field. In receive mode, the 8 bits immediately following the SOP field are interpreted as the length of the packet. When this bit is cleared no packet length field is transmitted. 8DR always sends the packet length field (LEN EN setting is ignored). GFSK requires user set LEN EN = 1. SOP Correlator Threshold. This is the receive data correlator threshold used when attempting to detect a SOP symbol. There is a single threshold for the SOP_CODE_ADR code. This threshold is applied independently to each of SOP1 and SOP2 fields. When SOP LEN is set, all 5 bits of this field are used. When SOP LEN is cleared, the most significant bit is disregarded. Typical applications configure SOP TH = 04h for SOP32 and SOP TH = 0Eh for SOP64.
Bit 6 Bit 5
Bits 4:0
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Mnemonic Bit Default Read/Write Function Bits 7:4 Bits 3:0 7 Not Used
DATA32_THOLD_ADR 6 Not Used 5 Not Used 4 Not Used 3 0 R/W 2 1 R/W TH32
Address 1 0 R/W 0 0
0x11
R/W
Not Used. 32 Chip Data PN Code Correlator Threshold. This register sets the correlator threshold used in DSSS modes when DATA CODE LENGTH (see TX_CFG_ADR) is set to 32. Typical applications configure TH32 = 05h.
Mnemonic Bit Default Read/Write Function Bits 7:5 Bits 4:0 7 Not Used
DATA64_THOLD_ADR 6 Not Used 5 Not Used 4 0 R/W 3 1 R/W 2 0 R/W TH64
Address 1 1 R/W 0 0
0x12
R/W
Not Used. 64 Chip Data PN Code Correlator Threshold. This register sets the correlator threshold used in DSSS modes when the DATA CODE LENGTH (see TX_CFG_ADR) is set to 64. Typical applications configure TH64 = 0Eh.
Mnemonic Bit Default Read/Write Function 7 0 R SOP 6 Not Used
RSSI_ADR 5 1 R LNA 4 0 R 3 0 R 2 0 R RSSI
Address 1 0 R 0 0 R
0x13
A Received Signal Strength Indicator (RSSI) reading is taken automatically when an SOP symbol is detected. In addition, an RSSI reading is taken whenever RSSI_ADR is read. The contents of this register are not valid after the device is configured for receive mode until either a SOP symbol is detected, or the register is (re)read. The conversion can occur as often as once every 12 s. The approximate slope of the curve is 1.9 dB/count, but is not guaranteed. If it is desired to measure the background RF signal strength on a channel before a packet has been received then the MCU should perform a "dummy" read of this register, the results of which should be discarded. This "dummy" read causes an RSSI measurement to be taken, and therefore subsequent readings of the register yield valid data. Bit 7 SOP RSSI Reading. When set, this bit indicates that the reading in the RSSI field was taken when a SOP symbol was detected. When cleared, this bit indicates that the reading stored in the RSSI field was triggered by a previous SPI read of this register. Bit 5 LNA State. This bit indicates the LNA state when the RSSI reading was taken. When cleared, this bit indicates that the LNA was disabled when the RSSI reading was taken; if set this bit indicates that the LNA was enabled when the RSSI reading was taken. RSSI Reading. This field indicates the instantaneous strength of the RF signal being received at the time that the RSSI reading was taken. A larger value indicates a stronger signal. The signal strength measured is for the RF signal on the configured channel, and is measured after the LNA stage.
Bits 4:0
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Mnemonic Bit Default Read/Write Function 7 1 R/W HEN 6 0 R/W
EOP_CTRL_ADR 5 1 R/W HINT 4 0 R/W 3 0 R/W 2 1 R/W EOP
Address 1 0 R/W 0 0
0x14
R/W
If the LEN EN bit is set, then the contents of this register have no effect. If the LEN EN bit is cleared, then this register is used to configure how an EOP (end of packet) condition is detected. Bit 7 EOP Hint Enable. When set, this bit causes an EOP to be detected if no correlations have been detected for the number of symbol periods set by the HINT field and the last two received bytes match the calculated CRC16 for all previously received bytes. Use of this mode reduces the chance of noncorrelations in the middle of a packet from being detected as an EOP condition. Bits 6:4 Bits 4:0 EOP Hint Symbol Count. The minimum number of symbols of consecutive noncorrelations at which the last two bytes are checked against the calculated CRC16 to detect an EOP condition. EOP Symbol Count. An EOP condition is deemed to exist when the number of consecutive noncorrelations is detected.
Mnemonic Bit Default Read/Write Function 7 0 R/W
CRC_SEED_LSB_ADR 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W
Address 1 0 R/W 0 0
0x15
R/W
CRC SEED LSB
The CRC16 seed allows different devices to generate or recognize different CRC16s for the same payload data. If a transmitter and receiver use a randomly selected CRC16 seed, the probability of correctly receiving data intended for a different receiver is 1/65535, even if the other transmitter/receiver are using the same SOP_CODE_ADR codes and channel. Bits 7:0 CRC16 Seed Least Significant Byte. The LSB of the starting value of the CRC16 calculation.
Mnemonic Bit Default Read/Write Function Bits 7:0 7 0 R/W
CRC_SEED_MSB_ADR 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W
Address 1 0 R/W 0 0
0x16
R/W
CRC SEED MSB CRC16 Seed Most Significant Byte. The MSB of the starting value of the CRC16 calculation.
Mnemonic Bit Default Read/Write Function Bits 7:0 7 R 6 R
TX_CRC_LSB_ADR 5 R 4 R TX CRC LSB 3 R 2 R
Address 1 R 0 R
0x17
Calculated CRC16 LSB. The LSB of the CRC16 that was calculated for the last transmitted packet. This value is only valid after packet transmission is complete.
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Mnemonic Bit Default Read/Write Function Bits 7:0 7 R 6 R
TX_CRC_MSB_ADR 5 R 4 R 3 R 2 R
Address 1 R 0 R
0x18
TX CRC MSB Calculated CRC16 MSB. The MSB of the CRC16 that was calculated for the last transmitted packet. This value is only valid after packet transmission is complete.
Mnemonic Bit Default Read/Write Function Bits 7:0 7 1 R 6 1 R
RX_CRC_LSB_ADR 5 1 R 4 1 R RX CRC LSB 3 1 R 2 1 R
Address 1 1 R 0 1 R
0x19
Received CRC16 LSB. The LSB of the CRC16 field extracted from the last received packet. This value is valid whether or not the CRC16 field matched the calculated CRC16 of the received packet.
Mnemonic Bit Default Read/Write Function Bits 7:0 7 1 R 6 1
RX_CRC_MSB_ADR 5 1 R 4 1 R 3 1 R 2 1 R
Address 1 1 R 0 1 R
0x1A
R
RX CRC MSB Received CRC16 MSB. The MSB of the CRC16 field extracted from the last received packet. This value is valid whether or not the CRC16 field matched the calculated CRC16 of the received packet.
Mnemonic Bit Default Read/Write Function Bits 7:0 7 0 R/W
TX_OFFSET_LSB_ADR 6 0 R 5 0 R 4 0 R STRIM LSB 3 0 R 2 0 R
Address 1 0 R 0 0 R
0x1B
The least significant 8 bits of the synthesizer offset value. This is a 12 bit 2's complement signed number, which may be used to offset the transmit frequency of the device by up to 1.5 MHz. A positive value increases the transmit frequency, and a negative value reduces the transmit frequency. A value of +1 increases the transmit frequency by 732.6 Hz; a value of -1 decreases the transmit frequency by 732.6 Hz. A value of 0x0555 increases the transmit frequency by 1 MHz; a value of 0xAAB decreases the transmit frequency by 1 MHz. Typically, this register is loaded with 0x55 during initialization. This feature is used to avoid the need to change the synthesizer frequency when switching between TX and RX. As the IF = 1 MHz the RX frequency is offset 1 MHz from the synthesizer frequency; therefore, transmitting with a 1 MHz offset allows the same synthesizer frequency to be used for both transmit and receive.
Synthesizer offset has no effect on receive frequency.
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Mnemonic Bit Default Read/Write Function Bits 7:4 Bits 3:0 7 Not Used
TX_OFFSET_MSB_ADR 6 Not Used 5 Not Used 4 Not Used 3 0 R/W 2 0 R/W
Address 1 0 R/W 0 0
0x1C
R/W
STRIM MSB
Not Used. The most significant 4 bits of the synthesizer trim value. Typically, this register is loaded with 0x05 during initialization.
Mnemonic Bit Default Read/Write Function Bits 7:6 Bit 5 Bits 4:3 Bits 2:1 Bit 0 7 0 W RSVD
MODE_OVERRIDE_ADR 6 0 W RSVD 5 0 W FRC SEN 4 0 W FRC AWAKE 3 0 W 2 Not Used
Address 1 Not Used 0 0 W
0x1D
RST
Reserved. Must be zero. Manually Initiate Synthesizer. Setting this bit forces the synthesizer to start. Clearing this bit has no effect. For this bit to operate correctly, the oscillator must be running before this bit is set. Force Awake. Force the device out of sleep mode. Setting both bits of this field forces the oscillator to keep running at all times regardless of the END STATE setting. Clearing both of these bits disables this function. Not Used. Reset. Setting this bit forces a full reset of the device. Clearing this bit has no effect.
Mnemonic Bit Default Read/Write Function Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 7 0 R/W ACK RX
RX_OVERRIDE_ADR 6 0 R/W RXTX DLY 5 0 R/W MAN RXACK 4 0 R/W FRC RXDR 3 0 R/W DIS CRC0 2 0 R/W DIS RXCRC
Address 1 0 R/W ACE 0 -
0x1E
Not Used
This register provides the ability to override some automatic features of the device. When this bit is set, the device uses the transmit synthesizer frequency rather than the receive synthesizer frequency for the given channel when automatically entering receive mode. When this bit is set and ACK EN is enabled, the transmission of the ACK packet is delayed by 20 s. Force Expected Packet Type. When this bit is set, and the device is in receive mode, the device is configured to receive an ACK packet at the data rate defined in TX_CFG_ADR. Force Receive Data Rate. When this bit is set, the receiver ignores the data rate encoded in the SOP symbol, and receives data at the data rate defined in TX_CFG_ADR. Reject packets with a zero-seed CRC16. Setting this bit causes the receiver to reject packets with a zero-seed, and accept only packets with a CRC16 that matches the seed in CRC_SEED_LSB_ADR and CRC_SEED_MSB_ADR. The RX CRC16 checker is disabled. If packets with CRC16 enabled are received, the CRC16 is treated as payload data and stored in the receive buffer. Accept Bad CRC16. Setting this bit causes the receiver to accept packets with a CRC16 that do not match the seed in CRC_SEED_LSB_ADR and CRC_SEED_MSB_ADR. An ACK is to be sent regardless of the condition of the received CRC16. Not Used.
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Mnemonic Bit Default Read/Write Function Bit 7 Bit 6 7 0 R/W ACK TX
TX_OVERRIDE_ADR 6 0 R/W FRC PRE 5 0 R/W RSVD 4 0 R/W MAN TXACK 3 0 R/W OVRD ACK 2 0 R/W DIS TXCRC
Address 1 0 R/W RSVD 0 0
0x1F
R/W TX INV
This register provides the ability to override some automatic features of the device. When this bit is set, the device uses the receive synthesizer frequency rather than the transmit synthesizer frequency for the given channel when automatically entering transmit mode. Force Preamble. When this bit is set, the device transmits a continuous repetition of the preamble pattern (see PREAMBLE_ADR) after TX GO is set. This mode is useful for some regulatory approval procedures. Firmware should set bit RST of MODE_OVERRIDE_ADR to exit this mode. Reserved. Must be zero. Transmit ACK Packet. When this bit is set, the device sends an ACK packet when TX GO is set. ACK Override. Use TX_CFG_ADR to determine the data rate and the CRC16 used when transmitting an ACK packet. Disable Transmit CRC16. When set, no CRC16 field is present at the end of transmitted packets. Reserved. Must be zero. TX Data Invert. When this bit is set the transmit bitstream is inverted.
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Mnemonic Bit Default Read/Write Function Bits 7:4 Bit 3 Bits 2:0 7 0 W RSVD 6 0 W RSVD
XTAL_CFG_ADR 5 0 W RSVD 4 0 W RSVD 3 0 W START DLY 2 0 W RSVD
Address 1 0 W RSVD 0 0 W
0x26
RSVD
This register provides the ability to override some automatic features of the device. Reserved. Must be zero. Crystal Startup Delay. Setting this bit, sets the crystal startup delay to 150 s to handle warm restarts of the crystal. Firmware MUST set this bit during initialization. Reserved. Must be zero.
Mnemonic Bit Default Read/Write Function Bits 7:2 Bit 1 Bit 0 7 0 W RSVD
CLK_OVERRIDE_ADR 6 0 W RSVD 5 0 W RSVD 4 0 W RSVD 3 0 W RSVD 2 0 W RSVD
Address 1 0 W RXF 0 0 W
0x27
RSVD
This register provides the ability to override some automatic features of the device. Reserved. Must be zero. Force Receive Clock. Streaming applications MUST set this bit during receive mode, otherwise this bit is cleared. Reserved. Must be zero.
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Mnemonic Bit Default Read/Write Function Bits 7:2 Bit 1 Bit 0 7 0 W RSVD 6 0 W RSVD
CLK_EN_ADR 5 0 W RSVD 4 0 W RSVD 3 0 W RSVD 2 0 W RSVD
Address 1 0 W RXF 0 0 W
0x28
RSVD
This register provides the ability to override some automatic features of the device. Reserved. Must be zero. Force Receive Clock Enable. Streaming applications MUST set this bit during initialization. Reserved. Must be zero.
Mnemonic Bit Default Read/Write Function Bits 7:6 Bit 5 Bits 4:0 7 0 W RSVD 6 0 W RSVD
RX_ABORT_ADR 5 0 W ABORT EN 4 0 W RSVD 3 0 W RSVD 2 0 W RSVD
Address 1 0 W RSVD 0 0 W
0x29
RSVD
This register provides the ability to override some automatic features of the device. Reserved. Must be zero. Receive Abort Enable. Typical applications disrupt any pending receive by first setting this bit, otherwise this bit is cleared. Reserved. Must be zero.
Mnemonic Bit Default Read/Write Function Bits 7:0 7 0 W
AUTO_CAL_TIME_ADR 6 0 W 5 0 W 4 0 W 3 0 W 2 0 W
Address 1 1 W 0 1 W
0x32
AUTO_CAL_TIME Auto Cal Time. Firmware MUST write 3Ch to this register during initialization.
This register provides the ability to override some automatic features of the device.
Mnemonic Bit Default Read/Write Function Bits 7:0 7 0 W
AUTO_CAL_OFFSET_ADR 6 0 W 5 0 W 4 0 W 3 0 W 2 0 W
Address 1 0 W 0 0 W
0x35
AUTO_CAL_OFFSET Auto Cal Offset. Firmware MUST write 14h to this register during initialization.
This register provides the ability to override some automatic features of the device.
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Mnemonic Bit Default Read/Write Function Bits 7:2 Bit 1 Bit 0 7 0 W RSVD
ANALOG_CTRL_ADR 6 0 W RSVD 5 0 W RSVD 4 0 W RSVD 3 0 W RSVD 2 0 W RSVD
Address 1 0 W RX INV 0 0 W
0x39
ALL SLOW
This register provides the ability to override some automatic features of the device. Reserved. Must be zero. Receive Invert. When set, the incoming receive data is inverted. Firmware MUST set this bit when interoperability with first generation devices is desired. All Slow. When set, the synth settling time for all channels is the same as for slow channels. It is recommended that firmware set this bit when using GFSK data rate mode.
Register Files Files are written to or read from using nonincrementing burst read or write transactions. In most cases, accessing a file may be destructive; the file must be completely read/written, otherwise the contents may be altered. When accessing file registers, the bytes are presented to the bus least significant byte first.
Mnemonic Length Default TX_BUFFER_ADR 16 Bytes 0xXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX Address R/W 0x20 W
The transmit buffer is a FIFO. Writing to this file adds a byte to the packet being sent. Writing more bytes to this file than the packet length in TX_LENGTH_ADR has no effect, and these bytes are lost. The FIFO accumulates data until it is reset using TX CLR in TX_CTRL_ADR. A previously sent packet, of 16 bytes or less, can be transmitted if TX_GO is set without resetting the FIFO. The contents of TX_BUFFER_ADR are not affected by the transmission of an Auto ACK.
Mnemonic Length Default
RX_BUFFER_ADR 16 Bytes 0xXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Address R/W
0x21 R
The receive buffer is a FIFO. Received bytes may be read from this file register at any time that it is not empty, but when reading from this file register before a packet has been completely received care must be taken to ensure that error packets (for example with bad CRC16) are handled correctly. When the receive buffer is configured to be overwritten by new packets (the alternative is for new packets to be discarded if the receive buffer is not empty), similar care must be taken to verify after the packet has been read from the buffer that no part of it was overwritten by a newly received packet while this file register is being read. When the VLD EN bit in RX_CFG_ADR is set, the bytes in this file register alternate--the first byte read is data, the second byte is a valid flag for each bit in the first byte, the third byte is data, the fourth byte valid flags, and so on. In SDR and DDR modes the valid flag for a bit is set if the correlation coefficient for the bit exceeds the correlator threshold, and is cleared if it does not. In 8DR mode, the MSB of a valid flags byte indicates whether or not the correlation coefficient of the corresponding received symbol exceeds the threshold. The seven LSBs contain the number of erroneous chips received for the data.
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Mnemonic Length Default
SOP_CODE_ADR 8 Bytes
0x17FF9E213690C782
Address R/W
0x22 R/W
When using 32 chip SOP_CODE_ADR codes, only the first four bytes of this register are used; in order to complete the file write process, these four bytes must be followed by four bytes of "dummy" data. However, a class of codes known as "multiplicative codes" may be used; there are 64 chip codes with good auto-correlation and cross-correlation properties where the least significant 32 chips themselves have good auto-correlation and cross-correlation properties when used as 32 chip codes. In this case the same eight byte value may be loaded into this file and used for both 32 chip and 64 chip SOP symbols. When reading this file, all eight bytes must be read; if fewer than eight bytes are read from the file, the contents of the file will have been rotated by the number of bytes read. This applies to writes, as well. Do not access or modify this register during Transmit or Receive. Recommended SOP Codes:
0x91CCF8E291CC373C 0x0FA239AD0FA1C59B 0x2AB18FD22AB064EF 0x507C26DD507CCD66 0x44F616AD44F6E15C 0x46AE31B646AECC5A 0x3CDC829E3CDC78A1 0x7418656F74198EB9 0x49C1DF6249C0B1DF 0x72141A7F7214E597
Mnemonic Length Default
DATA_CODE_ADR 16 Bytes
0x02F9939702FA5CE3012BF1DB0132BE6F
Address R/W
0x23 R/W
In GFSK mode, this file register is ignored. In 64 SDR mode, only the first eight bytes are used. In 32 DDR mode, only eight bytes are used. The format for these eight bytes: 0x00000000BBBBBBBB00000000AAAAAAAA, where `0' represents unused locations. Example: 0x00000000B2BB092B00000000B86BC0DC; where "B86BC0DC" represents AAAAAAAA, "00000000" represents unused locations, "B2BB092B" represents BBBBBBBB, and "00000000" represents unused locations. In 64 DDR and 8DR modes, all sixteen bytes are used. When reading this file, all sixteen bytes must be read; if fewer than sixteen bytes are read from the file, the contents of the file will have been rotated by the number of bytes read. This applies to writes, as well. Certain 16 byte sequences have been calculated that provide excellent auto-correlation and cross-correlation properties, and it is recommended that such sequences be used; the default value of this register is one such sequence. In typical applications, all devices use the same DATA_CODE_ADR codes, and devices and systems are addressed by using different SOP_CODE_ADR codes; in such cases it may never be necessary to change the contents of this register from the default value. Typical applications should use the default code. Do not access or modify this register during Transmit or Receive.
Mnemonic Length Default
PREAMBLE_ADR 3 Bytes 0x333302
Address R/W
0x24 R/W
1st byte - The number of repetitions of the preamble sequence that are to be transmitted. The preamble may be disabled by writing 0x00 to this byte. 2nd byte - Least significant eight chips of the preamble sequence 3rd byte - Most significant eight chips of the preamble sequence If using 64 SDR to communicate with CYWUSB69xx devices, set number of repetitions to four for optimum performance When reading this file, all three bytes must be read; if fewer than three bytes are read from the file, the contents of the file will have been rotated by the number of bytes read. This also applies to writes. Do not access or modify this register during Transmit or Receive.
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Mnemonic Length Default
MFG_ID_ADR 6 Bytes NA
Address R
0x25 R
To minimize ~190 A of current consumption (default), execute a "dummy" single-byte SPI write to this address with a zero data stage after the contents have been read. Non-zero to enable reading of fuses. Zero to disable reading fuses.
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Absolute Maximum Ratings
Storage Temperature .................................. -65C to +150C Ambient Temperature with Power Applied .. -55C to +125C Supply Voltage on any power supply pin relative to VSS ................................................ -0.3V to +3.9V DC Voltage to Logic Inputs[5] ................... -0.3V to VIO +0.3V DC Voltage applied to Outputs in High-Z State ......................................... -0.3V to VIO +0.3V Static Discharge Voltage (Digital)[6] ............................>2000V
Static Discharge Voltage (RF)[6] ................................. 1100V Latch Up Current .....................................+200 mA, -200 mA
Operating Conditions
VCC .....................................................................2.4V to 3.6V VIO ......................................................................1.8V to 3.6V VBAT ....................................................................1.8V to 3.6V TA (Ambient Temperature Under Bias) ............. 0C to +70C Ground Voltage.................................................................. 0V FOSC (Crystal Frequency)............................ 12MHz 30 ppm
DC Characteristics
(T = 25C, VBAT = 2.4V, PMU disabled, fOSC = 12.000000MHz)
Parameter VBAT VREG[7] VREG[7] VIO[8] VCC VOH1 VOH2 VOL VIH VIL IIL CIN ICC (GFSK)[10]
Description Battery Voltage PMU Output Voltage PMU Output Voltage VIO Voltage VCC Voltage Output High Voltage Condition 1 Output High Voltage Condition 2 Output Low Voltage Input High Voltage Input Low Voltage Input Leakage Current Pin Input Capacitance 0-70C 0-70C 2.4V mode 2.7V mode
Conditions
Min 1.8 2.4 2.7 1.8 2.4[9] VIO - 0.2 VIO - 0.4 0.7VIO 0
Typ 2.43 2.73
Max 3.6
Unit V V V
3.6 3.6 VIO VIO 0 0.45 VIO 0.3VIO 0.26 3.5 0.87 1.2 0.8 10 31.4 1.0 8.4 20.8 26.2 34.1 18.4 21.2 81 +1 10
V V V V V V V A pF mA mA A A mA mA mA mA mA mA mA %
At IOH = -100.0 A At IOH = -2.0 mA At IOL = 2.0 mA
0 < VIN < VIO except XTAL, RFN, RFP, RFBIAS
-1
Average TX ICC, 1 Mbps, slow channel PA = 5, 2 way, 4 bytes/10 ms Sleep Mode ICC Sleep Mode ICC Radio off, XTAL Active ICC during Synth Start ICC during Transmit ICC during Transmit ICC during Transmit ICC during Receive ICC during Receive PMU Boost Converter Efficiency PA = 5 (-5 dBm) PA = 6 (0 dBm) PA = 7 (+4 dBm) LNA off, ATT on LNA on, ATT off VBAT = 2.5V, VREG = 2.73V, ILOAD = 20 mA PMU enabled XOUT disabled
ICC (32-8DR)[10] Average TX ICC, 250 kbps, fast channel PA = 5, 2 way, 4 bytes/10 ms ISB[11] ISB[11] IDLE ICC Isynth TX ICC TX ICC TX ICC RX ICC RX ICC Boost Eff
Notes 5. It is permissible to connect voltages above VIO to inputs through a series resistor limiting input current to 1 mA. AC timing not guaranteed. 6. Human Body Model (HBM). 7. VREG depends on battery input voltage. 8. In sleep mode, the I/O interface voltage reference is VBAT. 9. In sleep mode, VCC min. can go as low as 1.8V. 10. Includes current drawn while starting crystal, starting synthesizer, transmitting packet (including SOP and CRC16), changing to receive mode, and receiving ACK handshake. Device is in sleep except during this transaction. 11. ISB is not guaranteed if any I/O pin is connected to voltages higher than VIO.
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DC Characteristics
(T = 25C, VBAT = 2.4V, PMU disabled, fOSC = 12.000000MHz)
(continued) Conditions VBAT = 1.8V, VREG = 2.73V, 0-50C, RX Mode VBAT = 1.8V, VREG = 2.73V, 50-70C, RX Mode Min Typ Max 15 10 Unit mA mA
Parameter ILOAD_EXT ILOAD_EXT
Description Average PMU External Load current Average PMU External Load current
AC Characteristics[12]
Table 6. SPI Interface[13] Parameter tSCK_CYC tSCK_HI tSCK_LO tDAT_SU tDAT_HLD tDAT_VAL tDAT_VAL_TRI tSS_SU tSS_HLD tSS_PW tSCK_SU tSCK_HLD tRESET SPI Clock Period SPI Clock High Time SPI Clock Low Time SPI Input Data Setup Time SPI Input Data Hold Time SPI Output Data Valid Time SPI Output Data Tri-state (MOSI from Slave Select Deassert) SPI Slave Select Setup Time before first positive edge of SCK[14] SPI Slave Select Hold Time after last negative edge of SCK SPI Slave Select Minimum Pulse Width SPI Slave Select Setup Time SPI SCK Hold Time Minimum RST Pin Pulse Width Figure 11. SPI Timing
tSCK_CYC SCK tSCK_SU nSS tSS_SU tDAT_SU MOSI input tDAT_VAL MISO tDAT_VAL_TRI tDAT_HLD tSS_HLD tSCK_HI tSCK_LO tSCK_HLD
Description
Min 238.1 100 100 25 10 0 10 10 20 10 10 10
Typ
Max
Unit ns ns ns ns ns
50 20
ns ns ns ns ns ns ns ns
MOSI output
Notes 12. AC values are not guaranteed if voltage on any pin exceed VIO. 13. CLOAD = 30 pF. 14. SCK must start low at the time SS goes LOW, otherwise the success of SPI transactions are not guaranteed.
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RF Characteristics
Table 7. Radio Parameters Parameter Description RF Frequency Range Note 15 Receiver (T = 25C, VCC = 3.0V, fOSC = 12.000000MHz, BER < 1E-3) Sensitivity 125 kbps 64-8DR BER 1E-3 Sensitivity 250 kbps 32-8DR Sensitivity Sensitivity GFSK LNA Gain ATT Gain Maximum Received Signal RSSI Value for PWRin -60 dBm RSSI Slope Interference Performance (CER 1E-3) Co-channel Interference rejection Carrier-to-Interference (C/I) Adjacent (1 MHz) channel selectivity C/I 1 MHz Adjacent (2 MHz) channel selectivity C/I 2 MHz Adjacent (> 3 MHz) channel selectivity C/I > 3 MHz Out-of-Band Blocking 30 MHz-12.75 MHz[16] Intermodulation Receive Spurious Emission 800 MHz 1.6 GHz 3.2 GHz Transmitter (T = 25C, VCC = 3.0V) Maximum RF Transmit Power Maximum RF Transmit Power Maximum RF Transmit Power Maximum RF Transmit Power RF Power Control Range RF Power Range Control Step Size Frequency Deviation Min Frequency Deviation Max Error Vector Magnitude (FSK error) Occupied Bandwidth Transmit Spurious Emission (PA = 7) In-band Spurious Second Channel Power (2 MHz) In-band Spurious Third Channel Power (>3 MHz) -38 -44 dBm dBm Seven steps, monotonic PN Code Pattern 10101010 PN Code Pattern 11110000 >0 dBm -6 dBc, 100 kHz ResBW 500 PA = 7 PA = 6 PA = 5 PA = 0 +2 -2 -7 4 0 -5 -35 39 5.6 270 323 10 876 +6 +2 -3 dBm dBm dBm dBm dB dB kHz kHz %rms kHz 100 kHz ResBW 100 kHz ResBW 100 kHz ResBW -79 -71 -65 dBm dBm dBm C = -60 dBm C = -60 dBm C = -60 dBm C = -67 dBm C = -67 dBm C = -64 dBm, f = 5,10 MHz 9 3 -30 -38 -30 -36 dB dB dB dB dBm dBm LNA On LNA On -15 BER 1E-3 CER 1E-3 BER 1E-3, ALL SLOW = 1 -80 Conditions Min 2.400 -97 -93 -87 -84 22.8 -31.7 -6 21 1.9 Typ Max 2.497 Unit GHz dBm dBm dBm dBm dB dB dBm Count dB/Count
Notes 15. Subject to regulation. 16. Exceptions F/3 & 5C/3.
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Table 7. Radio Parameters (continued) Parameter Description Non-Harmonically Related Spurs (800 MHz) Non-Harmonically Related Spurs (1.6 GHz) Non-Harmonically Related Spurs (3.2 GHz) Harmonic Spurs (Second Harmonic) Harmonic Spurs (Third Harmonic) Fourth and Greater Harmonics Power Management (Crystal PN# eCERA GF-1200008) Crystal Start to 10ppm Crystal Start to IRQ Synth Settle Synth Settle Synth Settle Link Turnaround Time Link Turnaround Time Link Turnaround Time Link Turnaround Time Max Packet Length Max Packet Length XSIRQ EN = 1 Slow channels Medium channels Fast channels GFSK 250 kbps 125 kbps <125 kbps <60 ppm crystal-to-crystal all modes except 64-DDR <60 ppm crystal-to-crystal 64-DDR 0.7 0.6 270 180 100 30 62 94 31 40 16 1.3 ms ms s s s s s s s bytes bytes Conditions Min Typ -38 -34 -47 -43 -48 -59 Max Unit dBm dBm dBm dBm dBm dBm
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Typical Operating Characteristics[17]
Transmit Power vs. Temperature (Vcc = 2.7v) 6 4 Output Power (dBm) 2 0 -2 -4 -6 -8 -10 -12 -14 0 20 40 Temp (deg C) 60 6 4 Output Power (dBm) 2 0 -2 -4 -6 -8 -10 -12 -14 2.4 2.6 2.8 Transmit Power vs. Vcc (PMU off)
Transmit Power vs. Channel 6
PA7 PA6
PA7
Output Power (dBm)
4 2 0 -2 -4 -6 -8 -10 -12 -14
3 3.2 3.4 3.6
PA7 PA6
PA6
PA5
PA5
PA5
PA4
PA4
PA4
0
20
40 Channel
60
80
Vcc
Typical RSSI Count vs Input Power
Average RSSI vs. Temperature (Rx signal = -70dBm) 19 18 20 19 18 RSSI Count 17 16 15 14 13 12 13 11 0 20 40 Temp (deg C) 60 10 2.4 2.6
Average RSSI vs. Vcc (Rx signal = -70dBm)
32
24 RSSI Count RSSI Count
17
16
LNA ON LNA OFF ATT ON LNA OFF
16 15 14
8
0 -120
12 -100 -80 -60 -40 -20 Input Power (dBm)
2.8
3 Vcc
3.2
3.4
3.6
RSSI vs. Channel (Rx signal = -70dBm) 18
Rx Sensitivity vs. Vcc (1Mbps CER) -80 Receiver Sensitivity (dBm) -82 -84 -86 -88 -90 -92 -94 2.4
Rx Sensitivity vs. Temperature (1Mbps CER) -80 Receiver Sensitivity (dBm) -82 -84 -86 -88 -90 -92 -94
16 14 RSSI Count 12 10 8 6 4 2 0 0 20 40 Channel 60 80
CER
CER
8DR32
8DR32
2.6
2.8
3 Vcc
3.2
3.4
3.6
0
20
40 Temp (deg C)
60
Receiver Sensitivity vs. Frequency Offset -80 Receiver Sensitivity (dBm) -82 -84 -86 -88 -90 -92 -94 -96 -98 -150
Receiver Sensitivity (dBm) -81 -83 -85 -87 -89 -91
Receiver Sensitivity vs Channel (3.0v, Room Temp) 20.0
Carrier to Interferer (Narrow band, LP modulation)
GFSK
10.0 0.0
GFSK
CER
C/I (dB)
-10.0 -20.0 -30.0 -40.0 -50.0 -60.0 -10
DDR32 8DR64
DDR32
-93 -95 0 20 40 Channel 60 80
8DR32
-100
-50
0
50
100
150
-5
0
5
10
Crystal Offset (ppm)
Channel Offset (MHz)
Note 17. With LNA on, ATT off, above -2dBm erroneous RSSI values may be read, cross-checking RSSI with LNA off/on is recommended for accurate readings.
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CYRF6936
BER vs. Data Threshold (32-DDR) (SOP Threshold = 5, C38 slow) 10 10
BER vs. Data Threshold (32-8DR) (SOP Threshold = 5, C38 slow)
GFSK vs. BER (SOP Threshold = 5, C38 slow) 100 10 1 %BER 0.1 0.01 0.001 0.0001 0.00001 -100
3
1
0 Thru 7
1
0
1 0.1 %BER 0.01 0.001 0.0001 0.00001 -100
6
0.1 %BER 0.01 0.001 0.0001 0.00001 -100
GFSK
-80 -60 -40 -20 0
-95
-90
-85
-80
-75
-70
-95
-90
-85
-80
-75
-70
Input Power (dBm)
Input Power (dBm)
Input Power (dBm)
ICC RX (LNA OFF) 21 OPERATING CURRENT (mA) OPERATING CURRENT (mA) 20.5 20 19.5 19 18.5 18 17.5 17 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 TEMPERATURE (C) 25 24.5
ICC RX (LNA ON) 9.2 9.1 9 8.9 8.8 8.7 8.6 8.5 8.4 8.3 8.2 8.1 8 7.9 7.8 0 5
ICC RX SYNTH
3.3V 3.0V 2.7V 2.4V
24 23.5 23 22.5 22 21.5 21 20.5 20 19.5 19 0 5
3.3V 3.0V 2.7V 2.4V
10 15 20 25 30 35 40 45 50 55 60 65 70 TEMPERATURE (C)
OPERATING CURRENT (mA)
3.3V 3.0V 2.7V 2.4V
10 15 20 25 30 35 40 45 50 55 60 65 70 TEMPERATURE (C)
ICC TX SYNTH 9.2 9.1 9 8.9 8.8 8.7 8.6 8.5 8.4 8.3 8.2 8.1 8 7.9 7.8 0 5 17 OPERATING CURRENT (mA) 16.5 16 15.5 15 14.5 14 10 15 20 25 30 35 40 45 50 55 60 65 70 TEMPERATURE (C) 0 5
ICC TX @ PA0 17.5 OPERATING CURRENT (mA)
ICC TX @ PA1
OPERATING CURRENT (mA)
3.3V 3.0V 2.7V 2.4V
3.3V 3.0V 2.7V 2.4V
17 16.5 16 15.5 15 14.5 14
3.3V 3.0V 2.7V 2.4V
10 15 20 25 30 35 40 45 50 55 60 65 70 TEMPERATURE (C)
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70 TEMPERATURE (C)
ICC TX @ PA2 18 OPERATING CURRENT (mA) 17.5 17 16.5 16 15.5 15 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 TEMPERATURE (C) 19
ICC TX @ PA3 20.5 OPERATING CURRENT (mA)
ICC TX @ PA4
3.3V 3.0V 2.7V 2.4V
OPERATING CURRENT (mA)
18.5 18 17.5 17 16.5 16 15.5 0
3.3V 3.0V 2.7V 2.4V
20 19.5 19 18.5 18 17.5 17 16.5
3.3V 3.0V 2.7V 2.4V
5 10 15 20 25 30 35 40 45 50 55 60 65 70 TEMPERATURE (C)
0
5 10 15 20 25 30 35 40 45 50 55 60 65 70 TEMPERATURE (C)
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ICC TX @ PA5 23.5 OPERATING CURRENT (mA) OPERATING CURRENT (mA) 23 22.5 22 21.5 21 20.5 20 19.5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 TEMPERATURE (C) 30
ICC TX @ PA6 40.5 40 39.5 39 38.5 38 37.5 37 36.5 36 35.5 35 34.5 34 33.5 33 32.5 0
ICC TX @ PA7
29 28.5 28 27.5 27 26.5 26 25.5 25 24.5 0
OPERATING CURRENT (mA)
3.3V 3.0V 2.7V 2.4V
29.5
3.3V 3.0V 2.7V 2.4V
3.3V 3.0V 2.7V 2.4V
5 10 15 20 25 30 35 40 45 50 55 60 65 70 TEMPERATURE (C)
5 10 15 20 25 30 35 40 45 50 55 60 65 70 TEMPERATURE (C)
AC Test Loads and Waveforms for Digital Pins
Figure 12. AC Test Loads and Waveforms for Digital Pins
AC Test Loads
OUTPUT 30 pF INCLUDING JIG AND SCOPE OUTPUT 5 pF
DC Test Load
VCC OUTPUT R2 R1
Max
INCLUDING JIG AND Typical SCOPE ALL INPUT PULSES VCC GND Rise time: 1 V/ns Equivalent to: THEVENIN EQUIVALENT RTH VTH OUTPUT
Parameter R1 R2 RTH VTH VCC
1071 937 500 1.4 3.00
Unit V V
90% 10%
90% 10% Fall time: 1 V/ns
Ordering Information
Table 8. Ordering Information Part Number CYRF6936-40LFXC Radio Transceiver Package Name Package Type 40 QFN 40 Quad Flat Package No Leads Lead-Free Operating Range Commercial
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CYRF6936
Package Description
Figure 13. 40-lead Pb-Free QFN 6 x 6 MM (Subcon Punch Type with 2.8 x 2.8 EPAD) LY40
TOP VIEW SIDE VIEW BOTTOM VIEW
C 0.05[0.002] MAX. 0.80[0.031] MAX. 0.20[0.008] REF. 0.18[0.007] 0.28[0.011] N PIN1 ID 0.20[0.008] R. 1 2 0.45[0.018] 2.8
0.08[0.003] A 5.90[0.232] 6.10[0.240] 5.70[0.224] 5.80[0.228] N 1 0.60[0.024] DIA. 2 1.00[0.039] MAX.
5.70[0.224] 5.80[0.228]
5.90[0.232] 6.10[0.240]
2.8
0-12
0.30[0.012] 0.50[0.020] C SEATING PLANE 4.45[0.175] 4.55[0.179]
0.50[0.020]
0.24[0.009] 0.60[0.024]
(4X)
NOTES: 1. HATCH IS SOLDERABLE EXPOSED AREA
2. REFERENCE JEDEC#: MO-220 3. PACKAGE WEIGHT: 0.086g 4. ALL DIMENSIONS ARE IN MM [MIN/MAX] 5. PACKAGE CODE PART # LY40 LF40 DESCRIPTION PB-FREE STANDARD
51-85190-*A
The recommended dimension of the PCB pad size for the E-PAD underneath the QFN is 3.5 mm x 3.5 mm (width x length). This document is subject to change, and may be found to contain errors of omission or changes in parameters. For feedback or technical support regarding Cypress WirelessUSB products, contact Cypress at www.cypress.com. WirelessUSB, PSoC, and enCoRe are trademarks of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.
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(c) Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
4.45[0.175] 4.55[0.179]
SOLDERABLE EXPOSED PAD
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Document History Page
Description Title: CYRF6936 WirelessUSBTM LP 2.4 GHz Radio SoC Document Number: 38-16015 REV. ** *A ECN NO. 307437 377574 Issue Date See ECN See ECN Orig. of Change TGE TGE New data sheet Preliminary release- - updated Section 1.0 - Features - updated Section 2.0 - Applications - added Section 3.0 - Applications Support - updated Section 4.0 - Functional Descriptions - updated Section 5.0 - Pin Description - added Figure 5-1 - updated Section 6.0 - Functional Overview - added Section 7.0 - Functional Block Overview - added Section 9.0 - Register Descriptions - updated Section 10.0 - Absolute Maximum Ratings - updated Section 11.0 - Operating Conditions - updated Section 12.0 - DC Characteristics - updated Section 13.0 - AC Characteristics - updated Section 14.0 - RF Characteristics - added Section 16.0 - Ordering Information ES-10 update- changed part no. - updated Section 9.0 - Register Descriptions - updated Section 12.0 - DC Characteristics - updated Section 14.0 - RF Characteristics ES-10 update- updated Section 4.0 - Functional Descriptions - updated Section 5.0 - Pin Descriptions - updated Section 6.0 - Functional Overview - updated Section 7.0 - Functional Block Overview - updated Section 9.0 - Register Descriptions - updated Section 10.0 - Absolute Maximum Ratings - updated Section 11.0 - Operating Conditions - updated Section 14.0 - RF Characteristics - updated Section 1.0 - Features - updated Section 5.0 - Pin Descriptions - updated Section 6.0 - Functional Overview - updated Section 7.0 - Functional Block Overview - updated Section 9.0 - Register Descriptions - added Section 10.0 - Recommended Radio Circuit Schematic - updated Section 11.0 - Absolute Maximum Ratings - updated Section 12.0 - Operating Conditions - updated Section 13.0 - DC Characteristics - updated Section 14.0 - AC Characteristics - updated Section 15.0 - RF Characteristics Final data sheet - removed "Preliminary" notation - updated Section 1.0 - Features - updated Section 5.0 - Pin Descriptions - updated Section 6.0 - Functional Overview - updated Section 7.0 - Functional Block Overview - updated Section 8.0 - Application Example - updated Section 9.0 - Register Descriptions - updated Section 12.0 - DC Characteristics - updated Section 13.0 - AC Characteristics - updated Section 14.0 - RF Characteristics - added Section 15.0 - Typical Operating Characteristics Description of Change
*B
398756
See ECN
TGE
*C
412778
See ECN
TGE
*D
435578
See ECN
TGE
*E *F
460458 487261
See ECN See ECN
BOO TGE
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Description Title: CYRF6936 WirelessUSBTM LP 2.4 GHz Radio SoC Document Number: 38-16015 *G 778236 See ECN OYR/ARI -modified radio function register descriptions -changed L/D pin description -footnotes added -changed RST Capacitor from 0.1uF to 0.47 uF -updated Figure 9, Recommended Circuit for Systems -updated Table 3, Recommended bill of materials for systems -updated package diagram from ** to *A
Document #: 38-16015 Rev. *G
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